commit 003c08418f841e6697b1b6ed81de94f536cf190d
author Timothy Hayes <timothy.hayes@arm.com> Tue Apr 21 18:58:03 2020 +0100
committer Pouya Fotouhi <pfotouhi@ucdavis.edu> Sat May 02 06:50:57 2020 +0000
tree c7b6ad2155a917db4df1e237934e8f3f14a25adf
parent 203efba46aff5598013aaaf5b088bd90be30414f

mem-ruby: MESI_Three_level prefetcher page crossing

This patch allows MESI_Three_level using the Ruby prefetcher to
safely cross page boundaries by determining if an address is bad
and cannot be mapped to a memory controller.

Change-Id: I675a13dfa6deb5b6a9f986ced5a3130436db911d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28048
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

configs/ruby/MESI_Three_Level.py

diff --git a/configs/ruby/MESI_Three_Level.py b/configs/ruby/MESI_Three_Level.py
index 0e9ef09..61d6c52 100644
--- a/configs/ruby/MESI_Three_Level.py
+++ b/configs/ruby/MESI_Three_Level.py
@@ -127,7 +127,7 @@
                 nonunit_filter = 256,
                 train_misses = 5,
                 num_startup_pfs = 4,
-                cross_page = False
+                cross_page = True
             )
 
             l0_cntrl = L0Cache_Controller(

src/mem/ruby/protocol/MESI_Three_Level-L0cache.sm

diff --git a/src/mem/ruby/protocol/MESI_Three_Level-L0cache.sm b/src/mem/ruby/protocol/MESI_Three_Level-L0cache.sm
index da89bf5..3639ef2 100644
--- a/src/mem/ruby/protocol/MESI_Three_Level-L0cache.sm
+++ b/src/mem/ruby/protocol/MESI_Three_Level-L0cache.sm
@@ -140,6 +140,7 @@
     PF_Load,         desc="Load request from prefetcher";
     PF_Ifetch,       desc="Instruction fetch request from prefetcher";
     PF_Store,        desc="Exclusive load request from prefetcher";
+    PF_Bad_Addr,     desc="Throw away prefetch request due to bad address generation";
   }
 
   // TYPES
@@ -323,7 +324,16 @@
   in_port(optionalQueue_in, RubyRequest, prefetchQueue, desc="...", rank = 2) {
     if (optionalQueue_in.isReady(clockEdge())) {
       peek(optionalQueue_in, RubyRequest) {
-        if (in_msg.Type == RubyRequestType:IFETCH) {
+        // first check for valid address
+        MachineID mid := mapAddressToMachine(in_msg.LineAddress, MachineType:Directory);
+        NodeID nid := machineIDToNodeID(mid);
+        int nidint := IDToInt(nid);
+        int numDirs := machineCount(MachineType:Directory);
+        if (nidint >= numDirs) {
+          Entry cache_entry := static_cast(Entry, "pointer", Dcache.getNullEntry());
+          TBE tbe := TBEs.getNullEntry();
+          trigger(Event:PF_Bad_Addr, in_msg.LineAddress, cache_entry, tbe);
+        } else if (in_msg.Type == RubyRequestType:IFETCH) {
           // Instruction Prefetch
           Entry icache_entry := getICacheEntry(in_msg.LineAddress);
           if (is_valid(icache_entry)) {
@@ -1164,4 +1174,8 @@
     o_popIncomingResponseQueue;
     kd_wakeUpDependents;
   }
+
+  transition(I, PF_Bad_Addr) {
+    pq_popPrefetchQueue;
+  }
 }