src/arch/arm/fastmodel/PL330_DMAC/PL330.lisa

/*
 * Copyright 2020 Google Inc.
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component PL330
{
    composition
    {
        pl330 : PL330_DMAC();

        // Clocks.
        clock1Hz : MasterClock();
        clockDiv : ClockDivider();

        // Bridges.

        // For DMA accesses.
        dma_out : PVBus2AMBAPV();

        // For register accesses.
        pio_s_in : AMBAPV2PVBus();
        pio_s_ns_in : AMBAPV2PVBus();
    }

    connection
    {
        // Outgoing DMA accesses.
        pl330.pvbus_m => dma_out.pvbus_s;
        dma_out.amba_pv_m => self.amba_m;

        // Incoming register accesses.
        self.amba_s => pio_s_in.amba_pv_s;
        pio_s_in.pvbus_m => pl330.pvbus_s;
        self.amba_s_ns => pio_s_ns_in.amba_pv_s;
        pio_s_ns_in.pvbus_m => pl330.pvbus_s_ns;

        // Clocks.
        clock1Hz.clk_out => clockDiv.clk_in;
        clockDiv.clk_out => pl330.clk_in;

        // Interrupts.
        pl330.irq_master_port => self.irq;
        pl330.irq_abort_master_port => self.irq_abort;
    }

    properties
    {
        component_type = "System";
    }

    slave port<ExportedClockRateControl> clock_rate_s
    {
        behavior set_mul_div(uint64_t mul, uint64_t div)
        {
            clockDiv.rate.set64(mul, div);
        }
    }

    master port<AMBAPV> amba_m;
    slave port<AMBAPV> amba_s;
    slave port<AMBAPV> amba_s_ns;

    master port<Signal> irq[32];
    master port<Signal> irq_abort;
}