src/arch/mips/decoder.hh

/*
 * Copyright (c) 2012 Google
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 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
 * redistributions in binary form must reproduce the above copyright
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 * neither the name of the copyright holders nor the names of its
 * contributors may be used to endorse or promote products derived from
 * this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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#ifndef __ARCH_MIPS_DECODER_HH__
#define __ARCH_MIPS_DECODER_HH__

#include "arch/generic/decode_cache.hh"
#include "arch/generic/decoder.hh"
#include "arch/mips/types.hh"
#include "base/logging.hh"
#include "base/types.hh"
#include "cpu/static_inst.hh"
#include "debug/Decode.hh"
#include "params/MipsDecoder.hh"

namespace gem5
{

class BaseISA;

namespace MipsISA
{

class Decoder : public InstDecoder
{
  protected:
    //The extended machine instruction being generated
    ExtMachInst emi;
    uint32_t machInst;

  public:
    Decoder(const MipsDecoderParams &p) : InstDecoder(p, &machInst)
    {}

    //Use this to give data to the decoder. This should be used
    //when there is control flow.
    void
    moreBytes(const PCStateBase &pc, Addr fetchPC) override
    {
        emi = letoh(machInst);
        instDone = true;
    }

  protected:
    /// A cache of decoded instruction objects.
    static GenericISA::BasicDecodeCache<Decoder, ExtMachInst> defaultCache;
    friend class GenericISA::BasicDecodeCache<Decoder, ExtMachInst>;

    StaticInstPtr decodeInst(ExtMachInst mach_inst);

    /// Decode a machine instruction.
    /// @param mach_inst The binary instruction to decode.
    /// @retval A pointer to the corresponding StaticInst object.
    StaticInstPtr
    decode(ExtMachInst mach_inst, Addr addr)
    {
        StaticInstPtr si = defaultCache.decode(this, mach_inst, addr);
        DPRINTF(Decode, "Decode: Decoded %s instruction: %#x\n",
                si->getName(), mach_inst);
        return si;
    }

  public:
    StaticInstPtr
    decode(PCStateBase &next_pc) override
    {
        if (!instDone)
            return NULL;
        instDone = false;
        return decode(emi, next_pc.instAddr());
    }
};

} // namespace MipsISA
} // namespace gem5

#endif // __ARCH_MIPS_DECODER_HH__