arch-arm: Fix linking error in aapcs64 unittests
This is fixing the undefined reference exposed by our nightly
run [1] by including the arch/arm/regs/int.cc source (needed
for the IntRegClassOps::flatten implementation) plus
sim/cur_tick.cc
[1]: https://www.mail-archive.com/gem5-dev@gem5.org/msg43249.html
Change-Id: I51a616ca2ef513f0068e531ebee17172d68cc738
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/64611
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
diff --git a/src/arch/arm/SConscript b/src/arch/arm/SConscript
index 5d27cee..6c359fb 100644
--- a/src/arch/arm/SConscript
+++ b/src/arch/arm/SConscript
@@ -49,8 +49,11 @@
# Note: This will need reconfigured for multi-isa. E.g., if this is
# incorporated: https://gem5-review.googlesource.com/c/public/gem5/+/52491
if env['USE_ARM_ISA']:
- GTest('aapcs64.test', 'aapcs64.test.cc', '../../base/debug.cc',
- '../../cpu/reg_class.cc', '../../sim/bufval.cc')
+ GTest('aapcs64.test', 'aapcs64.test.cc',
+ '../../base/debug.cc',
+ '../../cpu/reg_class.cc',
+ '../../sim/bufval.cc', '../../sim/cur_tick.cc',
+ 'regs/int.cc')
Source('decoder.cc', tags='arm isa')
Source('faults.cc', tags='arm isa')
Source('htm.cc', tags='arm isa')
