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/*
* Copyright (c) 2021 The Regents of the University of California.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution;
* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
#include "mem/port_terminator.hh"
namespace gem5 {
PortTerminator::PortTerminator(const PortTerminatorParams &params):
SimObject(params)
{
for (int i = 0; i < params.port_req_ports_connection_count; ++i) {
reqPorts.emplace_back(name() + ".req_ports" + std::to_string(i), this);
}
for (int j = 0; j < params.port_resp_ports_connection_count; ++j) {
reqPorts.emplace_back(name() + ".resp_ports" +
std::to_string(j), this);
}
}
Port &
PortTerminator::getPort(const std::string &if_name, PortID idx)
{
if (if_name == "req_ports" && idx < reqPorts.size()) {
return reqPorts[idx];
} else if (if_name == "resp_ports" && idx < respPorts.size()) {
return respPorts[idx];
} else {
return SimObject::getPort(if_name, idx);
}
}
}