components_library/memory/ddr3_1600_8x8.py

# Copyright (c) 2021 The Regents of the University of California
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from abc import abstractmethod
from typing import Optional

from m5.objects import DDR3_1600_8x8 as DIMM
from m5.objects import MemCtrl
from m5.params import Port, AddrRange

from .abstract_memory_system import AbstractMemorySystem
from ..boards.abstract_board import AbstractBoard

from ..utils.override import *

from typing import Tuple, Sequence, List


class DDR3_1600_8x8(AbstractMemorySystem):
    def __init__(self, size: Optional[str] = "512MiB") -> None:
        super(DDR3_1600_8x8, self).__init__()

        # The DDR3_1600_8x8 has a lot of variables with sensible defaults that
        # make sense for a DDR3_1600_8x8 device. Only the size has been
        # exposed.
        self._dram = DIMM(range=size)
        self.mem_cntrls = [MemCtrl(dram=self._dram)]

    @overrides(AbstractMemorySystem)
    def incorporate_memory(self, board: AbstractBoard) -> None:
        pass

    @overrides(AbstractMemorySystem)
    def get_mem_ports(self) -> Tuple[Sequence[AddrRange], Port]:
        return [(self._dram.range, ctrl.port) for ctrl in self.mem_cntrls]

    @overrides(AbstractMemorySystem)
    def get_memory_controllers(self) -> List[MemCtrl]:
        return self.mem_cntrls

    @overrides(AbstractMemorySystem)
    def get_memory_ranges(self):
        return [self._dram.range]