cpu: Consolidate and move the CPU's calls to TheISA::initCPU.
TheISA::initCPU is basically an ISA specific implementation of reset
logic on architectural state. As such, it only needs to be called if
we're not going to load a checkpoint, ie in initState.
Also, since the implementation was the same across all CPUs, this
change collapses all the individual implementations down into the base
CPU class.
Change-Id: Id68133fd7f31619c90bf7b3aad35ae20871acaa4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24189
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
diff --git a/src/cpu/base.cc b/src/cpu/base.cc
index ac0c7ac..5d6a857 100644
--- a/src/cpu/base.cc
+++ b/src/cpu/base.cc
@@ -321,6 +321,15 @@
}
void
+BaseCPU::initState()
+{
+ if (FullSystem && !params()->switched_out) {
+ for (auto *tc: threadContexts)
+ TheISA::initCPU(tc, tc->contextId());
+ }
+}
+
+void
BaseCPU::startup()
{
if (FullSystem) {
diff --git a/src/cpu/base.hh b/src/cpu/base.hh
index 5b15f41..f47bc8e 100644
--- a/src/cpu/base.hh
+++ b/src/cpu/base.hh
@@ -314,6 +314,7 @@
virtual ~BaseCPU();
void init() override;
+ void initState() override;
void startup() override;
void regStats() override;
diff --git a/src/cpu/kvm/base.cc b/src/cpu/kvm/base.cc
index 83cb04f..cda98b4 100644
--- a/src/cpu/kvm/base.cc
+++ b/src/cpu/kvm/base.cc
@@ -114,10 +114,6 @@
fatal("KVM: Multithreading not supported");
tc->initMemProxies(tc);
-
- // initialize CPU, including PC
- if (FullSystem && !switchedOut())
- TheISA::initCPU(tc, tc->contextId());
}
void
diff --git a/src/cpu/minor/cpu.cc b/src/cpu/minor/cpu.cc
index ddba0cd..5edc570 100644
--- a/src/cpu/minor/cpu.cc
+++ b/src/cpu/minor/cpu.cc
@@ -108,17 +108,6 @@
tc->initMemProxies(tc);
}
-
- /* Initialise CPUs (== threads in the ISA) */
- if (FullSystem && !params()->switched_out) {
- for (ThreadID thread_id = 0; thread_id < threads.size(); thread_id++)
- {
- ThreadContext *tc = getContext(thread_id);
-
- /* Initialize CPU, including PC */
- TheISA::initCPU(tc, cpuId());
- }
- }
}
/** Stats interface from SimObject (by way of BaseCPU) */
diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc
index 996f636..e4f1c04 100644
--- a/src/cpu/o3/cpu.cc
+++ b/src/cpu/o3/cpu.cc
@@ -599,13 +599,6 @@
thread[tid]->initMemProxies(thread[tid]->getTC());
}
- if (FullSystem && !params()->switched_out) {
- for (ThreadID tid = 0; tid < numThreads; tid++) {
- ThreadContext *src_tc = threadContexts[tid];
- TheISA::initCPU(src_tc, src_tc->contextId());
- }
- }
-
// Clear noSquashFromTC.
for (int tid = 0; tid < numThreads; ++tid)
thread[tid]->noSquashFromTC = false;
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index 566533c..06dd773 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -130,11 +130,6 @@
for (auto tc : threadContexts) {
// Initialise the ThreadContext's memory proxies
tc->initMemProxies(tc);
-
- if (FullSystem && !params()->switched_out) {
- // initialize CPU, including PC
- TheISA::initCPU(tc, tc->contextId());
- }
}
}