fastmodel: CortexA76 implements setResetAddr interface
Change-Id: I3612a62e2145d3442f01a69b21954fc00dd5ade9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/53327
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Earl Ou <shunhsingou@google.com>
diff --git a/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc b/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
index e9b468d..e77e734 100644
--- a/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
+++ b/src/arch/arm/fastmodel/CortexA76/cortex_a76.cc
@@ -95,6 +95,12 @@
set_evs_param("vfp-enable_at_reset", params().vfp_enable_at_reset);
}
+void
+CortexA76::setResetAddr(Addr addr, bool secure)
+{
+ evs_base_cpu->setResetAddr(num, addr, secure);
+}
+
Port &
CortexA76::getPort(const std::string &if_name, PortID idx)
{
diff --git a/src/arch/arm/fastmodel/CortexA76/cortex_a76.hh b/src/arch/arm/fastmodel/CortexA76/cortex_a76.hh
index 79d9eee..39f916e 100644
--- a/src/arch/arm/fastmodel/CortexA76/cortex_a76.hh
+++ b/src/arch/arm/fastmodel/CortexA76/cortex_a76.hh
@@ -74,6 +74,8 @@
void setCluster(CortexA76Cluster *_cluster, int _num);
+ void setResetAddr(Addr addr, bool secure = false) override;
+
Port &getPort(const std::string &if_name,
PortID idx=InvalidPortID) override;
};
diff --git a/src/arch/arm/fastmodel/CortexA76/evs.cc b/src/arch/arm/fastmodel/CortexA76/evs.cc
index 4b25014..935d139 100644
--- a/src/arch/arm/fastmodel/CortexA76/evs.cc
+++ b/src/arch/arm/fastmodel/CortexA76/evs.cc
@@ -67,7 +67,7 @@
void
ScxEvsCortexA76<Types>::setResetAddr(int core, Addr addr, bool secure)
{
- panic("Not implemented for A76.");
+ this->rvbaraddr[core]->set_state(0, addr);
}
template <class Types>
@@ -91,6 +91,8 @@
new SignalReceiver(csprintf("vcpumntirq[%d]", i)));
cntpnsirq.emplace_back(
new SignalReceiver(csprintf("cntpnsirq[%d]", i)));
+ rvbaraddr.emplace_back(new SignalInitiator<uint64_t>(
+ csprintf("rvbaraddr[%d]", i).c_str()));
Base::cnthpirq[i].bind(cnthpirq[i]->signal_in);
Base::cnthvirq[i].bind(cnthvirq[i]->signal_in);
@@ -101,6 +103,7 @@
Base::pmuirq[i].bind(pmuirq[i]->signal_in);
Base::vcpumntirq[i].bind(vcpumntirq[i]->signal_in);
Base::cntpnsirq[i].bind(cntpnsirq[i]->signal_in);
+ rvbaraddr[i]->bind(Base::rvbaraddr[i]);
}
clockRateControl.bind(this->clock_rate_s);
diff --git a/src/arch/arm/fastmodel/CortexA76/evs.hh b/src/arch/arm/fastmodel/CortexA76/evs.hh
index 37f8363..7c834d0 100644
--- a/src/arch/arm/fastmodel/CortexA76/evs.hh
+++ b/src/arch/arm/fastmodel/CortexA76/evs.hh
@@ -69,10 +69,13 @@
ClockRateControlInitiatorSocket clockRateControl;
ClockRateControlInitiatorSocket periphClockRateControl;
- typedef sc_gem5::TlmTargetBaseWrapper<
+ using TlmGicTarget = sc_gem5::TlmTargetBaseWrapper<
64, svp_gicv3_comms::gicv3_comms_fw_if,
svp_gicv3_comms::gicv3_comms_bw_if, 1,
- sc_core::SC_ONE_OR_MORE_BOUND> TlmGicTarget;
+ sc_core::SC_ONE_OR_MORE_BOUND>;
+
+ template <typename T>
+ using SignalInitiator = amba_pv::signal_master_port<T>;
AmbaInitiator amba;
std::vector<std::unique_ptr<TlmGicTarget>> redist;
@@ -86,6 +89,7 @@
std::vector<std::unique_ptr<SignalReceiver>> pmuirq;
std::vector<std::unique_ptr<SignalReceiver>> vcpumntirq;
std::vector<std::unique_ptr<SignalReceiver>> cntpnsirq;
+ std::vector<std::unique_ptr<SignalInitiator<uint64_t>>> rvbaraddr;
CortexA76Cluster *gem5CpuCluster;
diff --git a/src/arch/arm/fastmodel/CortexA76/x1/x1.lisa b/src/arch/arm/fastmodel/CortexA76/x1/x1.lisa
index 04dae41..b83efc6 100644
--- a/src/arch/arm/fastmodel/CortexA76/x1/x1.lisa
+++ b/src/arch/arm/fastmodel/CortexA76/x1/x1.lisa
@@ -57,6 +57,9 @@
core.pmuirq => self.pmuirq;
core.vcpumntirq => self.vcpumntirq;
+ // Core reset addrs.
+ self.rvbaraddr => core.rvbaraddr;
+
// Clocks.
clock1Hz.clk_out => clockDiv.clk_in;
clock1Hz.clk_out => clockDivPeriph.clk_in;
@@ -96,4 +99,5 @@
master port<Signal> pmuirq[1];
master port<Signal> vcpumntirq[1];
master port<Signal> cntpnsirq[1];
+ slave port<Value_64> rvbaraddr[1];
}
diff --git a/src/arch/arm/fastmodel/CortexA76/x2/x2.lisa b/src/arch/arm/fastmodel/CortexA76/x2/x2.lisa
index 0279140..4ab0b07 100644
--- a/src/arch/arm/fastmodel/CortexA76/x2/x2.lisa
+++ b/src/arch/arm/fastmodel/CortexA76/x2/x2.lisa
@@ -57,6 +57,9 @@
core.pmuirq => self.pmuirq;
core.vcpumntirq => self.vcpumntirq;
+ // Core reset addrs.
+ self.rvbaraddr => core.rvbaraddr;
+
// Clocks.
clock1Hz.clk_out => clockDiv.clk_in;
clock1Hz.clk_out => clockDivPeriph.clk_in;
@@ -96,4 +99,5 @@
master port<Signal> pmuirq[2];
master port<Signal> vcpumntirq[2];
master port<Signal> cntpnsirq[2];
+ slave port<Value_64> rvbaraddr[2];
}
diff --git a/src/arch/arm/fastmodel/CortexA76/x3/x3.lisa b/src/arch/arm/fastmodel/CortexA76/x3/x3.lisa
index b18b102..7625769 100644
--- a/src/arch/arm/fastmodel/CortexA76/x3/x3.lisa
+++ b/src/arch/arm/fastmodel/CortexA76/x3/x3.lisa
@@ -57,6 +57,9 @@
core.pmuirq => self.pmuirq;
core.vcpumntirq => self.vcpumntirq;
+ // Core reset addrs.
+ self.rvbaraddr => core.rvbaraddr;
+
// Clocks.
clock1Hz.clk_out => clockDiv.clk_in;
clock1Hz.clk_out => clockDivPeriph.clk_in;
@@ -96,4 +99,5 @@
master port<Signal> pmuirq[3];
master port<Signal> vcpumntirq[3];
master port<Signal> cntpnsirq[3];
+ slave port<Value_64> rvbaraddr[3];
}
diff --git a/src/arch/arm/fastmodel/CortexA76/x4/x4.lisa b/src/arch/arm/fastmodel/CortexA76/x4/x4.lisa
index c7f1cb2..3e67719 100644
--- a/src/arch/arm/fastmodel/CortexA76/x4/x4.lisa
+++ b/src/arch/arm/fastmodel/CortexA76/x4/x4.lisa
@@ -57,6 +57,9 @@
core.pmuirq => self.pmuirq;
core.vcpumntirq => self.vcpumntirq;
+ // Core reset addrs.
+ self.rvbaraddr => core.rvbaraddr;
+
// Clocks.
clock1Hz.clk_out => clockDiv.clk_in;
clock1Hz.clk_out => clockDivPeriph.clk_in;
@@ -96,4 +99,5 @@
master port<Signal> pmuirq[4];
master port<Signal> vcpumntirq[4];
master port<Signal> cntpnsirq[4];
+ slave port<Value_64> rvbaraddr[4];
}
