commit 0f50b6252bceb49547dfa05c3eba1a0e1e209d7d
author Giacomo Travaglini <giacomo.travaglini@arm.com> Mon Jun 24 16:31:08 2019 +0100
committer Giacomo Travaglini <giacomo.travaglini@arm.com> Wed Jun 26 11:58:55 2019 +0000
tree 92008608ac68f69348f867e4ae422f28093fa3a6
parent f82f1dd81b9e2342e1c43fe5c413626c1cde996f

dev-arm: Remove un-needed Q_CONS_PROD_MASK macro

Change-Id: I858d7eea088bbdd2dc12123e21e59991c896597f
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Michiel Van Tol <michiel.vantol@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19310
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

src/dev/arm/smmu_v3_cmdexec.cc

diff --git a/src/dev/arm/smmu_v3_cmdexec.cc b/src/dev/arm/smmu_v3_cmdexec.cc
index 494c867..48896bf 100644
--- a/src/dev/arm/smmu_v3_cmdexec.cc
+++ b/src/dev/arm/smmu_v3_cmdexec.cc
@@ -56,8 +56,7 @@
         busy = true;
 
         while (true) {
-            int sizeMask =
-                mask(smmu.regs.cmdq_base & Q_BASE_SIZE_MASK) & Q_CONS_PROD_MASK;
+            int sizeMask = mask(smmu.regs.cmdq_base & Q_BASE_SIZE_MASK);
 
             if ((smmu.regs.cmdq_cons & sizeMask) ==
                     (smmu.regs.cmdq_prod & sizeMask))

src/dev/arm/smmu_v3_defs.hh

diff --git a/src/dev/arm/smmu_v3_defs.hh b/src/dev/arm/smmu_v3_defs.hh
index f74f819..2070e1d 100644
--- a/src/dev/arm/smmu_v3_defs.hh
+++ b/src/dev/arm/smmu_v3_defs.hh
@@ -92,7 +92,6 @@
     VMT_BASE_ADDR_MASK = 0x0000ffffffffffe0ULL,
     VMT_BASE_SIZE_MASK = 0x000000000000001fULL,
 
-    Q_CONS_PROD_MASK   = 0x00000000000fffffULL,
     Q_BASE_ADDR_MASK   = 0x0000ffffffffffe0ULL,
     Q_BASE_SIZE_MASK   = 0x000000000000001fULL,
 

src/dev/arm/smmu_v3_transl.cc

diff --git a/src/dev/arm/smmu_v3_transl.cc b/src/dev/arm/smmu_v3_transl.cc
index f1e1fb1..c1a7ed1 100644
--- a/src/dev/arm/smmu_v3_transl.cc
+++ b/src/dev/arm/smmu_v3_transl.cc
@@ -1280,8 +1280,7 @@
 void
 SMMUTranslationProcess::sendEvent(Yield &yield, const SMMUEvent &ev)
 {
-    int sizeMask = mask(smmu.regs.eventq_base & Q_BASE_SIZE_MASK) &
-            Q_CONS_PROD_MASK;
+    int sizeMask = mask(smmu.regs.eventq_base & Q_BASE_SIZE_MASK);
 
     if (((smmu.regs.eventq_prod+1) & sizeMask) ==
             (smmu.regs.eventq_cons & sizeMask))