src/arch/riscv/isa/operands.isa

// -*- mode:c++ -*-

// Copyright (c) 2015 RISC-V Foundation
// Copyright (c) 2016 The University of Virginia
// Copyright (c) 2020 Barkhausen Institut
// All rights reserved.
//
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def operand_types {{
    'sb' : 'int8_t',
    'ub' : 'uint8_t',
    'sh' : 'int16_t',
    'uh' : 'uint16_t',
    'sw' : 'int32_t',
    'uw' : 'uint32_t',
    'sd' : 'int64_t',
    'ud' : 'uint64_t',
    'sf' : 'float',
    'df' : 'double'
}};

def operands {{
#General Purpose Integer Reg Operands
    'Rd': IntRegOp('ud', 'RD', 'IsInteger', 1),
    'Rs1': IntRegOp('ud', 'RS1', 'IsInteger', 2),
    'Rs2': IntRegOp('ud', 'RS2', 'IsInteger', 3),
    'Rt': IntRegOp('ud', 'AMOTempReg', 'IsInteger', 4),
    'Rc1': IntRegOp('ud', 'RC1', 'IsInteger', 2),
    'Rc2': IntRegOp('ud', 'RC2', 'IsInteger', 3),
    'Rp1': IntRegOp('ud', 'RP1 + 8', 'IsInteger', 2),
    'Rp2': IntRegOp('ud', 'RP2 + 8', 'IsInteger', 3),
    'ra': IntRegOp('ud', 'ReturnAddrReg', 'IsInteger', 1),
    'sp': IntRegOp('ud', 'StackPointerReg', 'IsInteger', 2),

    'a0': IntRegOp('ud', '10', 'IsInteger', 1),

    'Fd': FloatRegOp('df', 'FD', 'IsFloating', 1),
    'Fd_bits': FloatRegOp('ud', 'FD', 'IsFloating', 1),
    'Fs1': FloatRegOp('df', 'FS1', 'IsFloating', 2),
    'Fs1_bits': FloatRegOp('ud', 'FS1', 'IsFloating', 2),
    'Fs2': FloatRegOp('df', 'FS2', 'IsFloating', 3),
    'Fs2_bits': FloatRegOp('ud', 'FS2', 'IsFloating', 3),
    'Fs3': FloatRegOp('df', 'FS3', 'IsFloating', 4),
    'Fs3_bits': FloatRegOp('ud', 'FS3', 'IsFloating', 4),
    'Fc1': FloatRegOp('df', 'FC1', 'IsFloating', 1),
    'Fc1_bits': FloatRegOp('ud', 'FC1', 'IsFloating', 1),
    'Fc2': FloatRegOp('df', 'FC2', 'IsFloatReg', 2),
    'Fc2_bits': FloatRegOp('ud', 'FC2', 'IsFloating', 2),
    'Fp2': FloatRegOp('df', 'FP2 + 8', 'IsFloating', 2),
    'Fp2_bits': FloatRegOp('ud', 'FP2 + 8', 'IsFloating', 2),

#Memory Operand
    'Mem': MemOp('ud', None, (None, 'IsLoad', 'IsStore'), 5),

#Program Counter Operands
    'PC': PCStateOp('ud', 'pc', (None, None, 'IsControl'), 7),
    'NPC': PCStateOp('ud', 'npc', (None, None, 'IsControl'), 8),
}};