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# -*- coding: utf-8 -*-
# Copyright (c) 2015 Jason Power
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""" This file creates a system with Ruby caches and runs the ruby random tester
See Part 3 in the Learning gem5 book:
http://gem5.org/documentation/learning_gem5/part3/MSIintro
IMPORTANT: If you modify this file, it's likely that the Learning gem5 book
also needs to be updated. For now, email Jason <jason@lowepower.com>
"""
from __future__ import print_function
from __future__ import absolute_import
# import the m5 (gem5) library created when gem5 is built
import m5
# import all of the SimObjects
from m5.objects import *
from test_caches import TestCacheSystem
# create the system we are going to simulate
system = System()
# Set the clock fequency of the system (and all of its children)
system.clk_domain = SrcClockDomain()
system.clk_domain.clock = '1GHz'
system.clk_domain.voltage_domain = VoltageDomain()
# Set up the system
system.mem_mode = 'timing' # Use timing accesses
system.mem_ranges = [AddrRange('512MB')] # Create an address range
# Create the tester
system.tester = RubyTester(checks_to_complete = 100,
wakeup_frequency = 10,
num_cpus = 2)
# Create a simple memory controller and connect it to the membus
system.mem_ctrl = SimpleMemory(latency="50ns", bandwidth="0GB/s")
system.mem_ctrl.range = system.mem_ranges[0]
# Create the Ruby System
system.caches = TestCacheSystem()
system.caches.setup(system, system.tester, [system.mem_ctrl])
# set up the root SimObject and start the simulation
root = Root(full_system = False, system = system)
# Not much point in this being higher than the L1 latency
m5.ticks.setGlobalFrequency('1ns')
# instantiate all of the objects we've created above
m5.instantiate()
print("Beginning simulation!")
exit_event = m5.simulate()
print('Exiting @ tick {} because {}'.format(
m5.curTick(), exit_event.getCause())
)