src/mem/HBMCtrl.py

# Copyright (c) 2022 The Regents of the University of California
# All Rights Reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

from m5.params import *
from m5.proxy import *
from m5.objects.MemCtrl import *

# HBMCtrl manages two pseudo channels of HBM2

class HBMCtrl(MemCtrl):
    type = 'HBMCtrl'
    cxx_header = "mem/hbm_ctrl.hh"
    cxx_class = 'gem5::memory::HBMCtrl'

    # HBMCtrl uses the SimpleMemCtlr's interface
    # `dram` as the first pseudo channel, the second
    # pseudo channel interface is following
    # HBMCtrl has been tested with two HBM_2000_4H_1x64 interfaces
    dram_2 = Param.DRAMInterface("DRAM memory interface")

    # For mixed traffic, HBMCtrl with HBM_2000_4H_1x64 interfaaces
    # gives the best results with following min_r/w_per_switch
    min_reads_per_switch = 64
    min_writes_per_switch = 64

    partitioned_q = Param.Bool(True, "split queues for pseudo channels")