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# Copyright (c) 2021 The Regents of the University of California
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from m5.objects import Port, PortTerminator
from ...utils.override import overrides
from .cpu_types import CPUTypes
from .abstract_core import AbstractCore
from ...isas import ISA
from ...utils.requires import requires
from typing import Optional
class AbstractGeneratorCore(AbstractCore):
"""The abstract generator core
Generator cores are cores that can replace the processing cores to allow
for testing computer systems in gem5. The abstract class
AbstractGeneratorCore defines the external interface that every generator
core must implement. Certain generator cores might need to extend this
interface to fit their requirements.
"""
def __init__(self):
"""
Create an AbstractCore with the CPUType of Timing. Also, setup a
dummy generator object to connect to icache
"""
# TODO: Remove the CPU Type parameter. This not needed.
# Jira issue here: https://gem5.atlassian.net/browse/GEM5-1031
super().__init__(CPUTypes.TIMING)
self.port_end = PortTerminator()
@overrides(AbstractCore)
def get_isa(self) -> ISA:
return ISA.NULL
@overrides(AbstractCore)
def connect_icache(self, port: Port) -> None:
"""
Generator cores only have one request port which we will connect to
the data cache not the icache. Just connect the icache to the
PortTerminator here.
"""
self.port_end.req_ports = port
@overrides(AbstractCore)
def connect_walker_ports(self, port1: Port, port2: Port) -> None:
"""
Since generator cores are not used in full system mode, no need to
connect them to walker ports. connect them to PortTerminator here.
"""
self.port_end.req_ports = port1
self.port_end.req_ports = port2
@overrides(AbstractCore)
def set_workload(self, process: "Process") -> None:
"""
Generator cores do not need any workload assigned to them, as they
generate their own synthetic workload (synthetic traffic). Just pass
here.
:param process: The process to execute during simulation.
"""
pass
@overrides(AbstractCore)
def connect_interrupt(
self,
interrupt_requestor: Optional[Port] = None,
interrupt_responce: Optional[Port] = None,
) -> None:
"""
Since generator cores are not used in full system mode, no need to
connect them to walker ports. Just pass here.
"""
pass