| commit | 1e1d5e247ecc55dc3d92875ca5ec6ae70879d8c1 | [log] [tgz] |
|---|---|---|
| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | Mon Sep 02 15:28:58 2019 +0100 |
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | Fri Sep 06 20:00:34 2019 +0000 |
| tree | 4d96d7b40b555524d74eaeda92bc45bb9e4a3f7a | |
| parent | 96fdb20871b16782ed405e58e9d9cc005d661b21 [diff] |
arch-arm: MISCREG_ICC_BPR1_EL1 using AA64 banking Change-Id: Ib30c7a49490f05f88ddfd7572dd360cb92647f81 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20625 Maintainer: Andreas Sandberg <andreas.sandberg@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc index 0bae018..76a9917 100644 --- a/src/arch/arm/miscregs.cc +++ b/src/arch/arm/miscregs.cc
@@ -4603,7 +4603,7 @@ .allPrivileges().exceptUserMode().writes(0) .mapsTo(MISCREG_ICC_HPPIR1); InitReg(MISCREG_ICC_BPR1_EL1) - .banked() + .banked64() .mapsTo(MISCREG_ICC_BPR1); InitReg(MISCREG_ICC_BPR1_EL1_NS) .bankedChild()