| # Copyright (c) 2021 The Regents of the University of California |
| # All rights reserved. |
| # |
| # Redistribution and use in source and binary forms, with or without |
| # modification, are permitted provided that the following conditions are |
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| # notice, this list of conditions and the following disclaimer; |
| # redistributions in binary form must reproduce the above copyright |
| # notice, this list of conditions and the following disclaimer in the |
| # documentation and/or other materials provided with the distribution; |
| # neither the name of the copyright holders nor the names of its |
| # contributors may be used to endorse or promote products derived from |
| # this software without specific prior written permission. |
| # |
| # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
| # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
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| |
| """Simple memory controllers |
| """ |
| |
| from ...utils.override import overrides |
| from m5.util.convert import toMemorySize |
| from typing import List, Sequence, Tuple |
| from ..boards.abstract_board import AbstractBoard |
| from .abstract_memory_system import AbstractMemorySystem |
| from m5.objects import AddrRange, MemCtrl, Port, SimpleMemory |
| |
| class SingleChannelSimpleMemory(AbstractMemorySystem): |
| """A class to implement single channel memory system using SimpleMemory |
| |
| This class takes latency, latency variation, and bandwidth and configures |
| a memory with those values. It could be used for studies that do not target |
| memory subsystem design. |
| """ |
| |
| def __init__( |
| self, latency: str, latency_var: str, bandwidth: str, size: str |
| ): |
| """ |
| :param latency: The average of request to response latency. |
| :param latency_var: The variance of request to response latency. |
| :param bandwidth: Combined read and write bandwidth. |
| :param size: Size of the memory. |
| """ |
| super().__init__() |
| |
| self.module = SimpleMemory( |
| latency=latency, latency_var=latency_var, bandwidth=bandwidth |
| ) |
| self._size = toMemorySize(size) |
| |
| @overrides(AbstractMemorySystem) |
| def incorporate_memory(self, board: AbstractBoard) -> None: |
| pass |
| |
| @overrides(AbstractMemorySystem) |
| def get_mem_ports(self) -> Sequence[Tuple[AddrRange, Port]]: |
| return [(self.module.range, self.module.port)] |
| |
| @overrides(AbstractMemorySystem) |
| def get_memory_controllers(self) -> List[MemCtrl]: |
| return [self.module] |
| |
| @overrides(AbstractMemorySystem) |
| def get_size(self) -> int: |
| return self._size |
| |
| @overrides(AbstractMemorySystem) |
| def set_memory_range(self, ranges: List[AddrRange]) -> None: |
| if len(ranges) != 1 or ranges[0].size() != self._size: |
| raise Exception( |
| "Simple single channel memory controller requires a single " |
| "range which matches the memory's size." |
| ) |
| self.module.range = ranges[0] |