arch-arm: Use scoped enum for ExceptionClass
Change-Id: I42ce3c31dfe89b75658db4a79c6a29a43fd0d82b
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/64411
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc
index 76320f6..d2696a2 100644
--- a/src/arch/arm/faults.cc
+++ b/src/arch/arm/faults.cc
@@ -205,106 +205,106 @@
// Some dummy values (the reset vector has an IMPLEMENTATION DEFINED
// location in AArch64)
"Reset", 0x000, 0x000, 0x000, 0x000, 0x000, MODE_SVC,
- 0, 0, 0, 0, false, true, true, EC_UNKNOWN
+ 0, 0, 0, 0, false, true, true, ExceptionClass::UNKNOWN
);
template<> ArmFault::FaultVals ArmFaultVals<UndefinedInstruction>::vals(
"Undefined Instruction", 0x004, 0x000, 0x200, 0x400, 0x600, MODE_UNDEFINED,
- 4, 2, 0, 0, true, false, false, EC_UNKNOWN
+ 4, 2, 0, 0, true, false, false, ExceptionClass::UNKNOWN
);
template<> ArmFault::FaultVals ArmFaultVals<SupervisorCall>::vals(
"Supervisor Call", 0x008, 0x000, 0x200, 0x400, 0x600, MODE_SVC,
- 4, 2, 4, 2, true, false, false, EC_SVC_TO_HYP
+ 4, 2, 4, 2, true, false, false, ExceptionClass::SVC_TO_HYP
);
template<> ArmFault::FaultVals ArmFaultVals<SecureMonitorCall>::vals(
"Secure Monitor Call", 0x008, 0x000, 0x200, 0x400, 0x600, MODE_MON,
- 4, 4, 4, 4, false, true, true, EC_SMC_TO_HYP
+ 4, 4, 4, 4, false, true, true, ExceptionClass::SMC_TO_HYP
);
template<> ArmFault::FaultVals ArmFaultVals<HypervisorCall>::vals(
"Hypervisor Call", 0x008, 0x000, 0x200, 0x400, 0x600, MODE_HYP,
- 4, 4, 4, 4, true, false, false, EC_HVC
+ 4, 4, 4, 4, true, false, false, ExceptionClass::HVC
);
template<> ArmFault::FaultVals ArmFaultVals<PrefetchAbort>::vals(
"Prefetch Abort", 0x00C, 0x000, 0x200, 0x400, 0x600, MODE_ABORT,
- 4, 4, 0, 0, true, true, false, EC_PREFETCH_ABORT_TO_HYP
+ 4, 4, 0, 0, true, true, false, ExceptionClass::PREFETCH_ABORT_TO_HYP
);
template<> ArmFault::FaultVals ArmFaultVals<DataAbort>::vals(
"Data Abort", 0x010, 0x000, 0x200, 0x400, 0x600, MODE_ABORT,
- 8, 8, 0, 0, true, true, false, EC_DATA_ABORT_TO_HYP
+ 8, 8, 0, 0, true, true, false, ExceptionClass::DATA_ABORT_TO_HYP
);
template<> ArmFault::FaultVals ArmFaultVals<VirtualDataAbort>::vals(
"Virtual Data Abort", 0x010, 0x000, 0x200, 0x400, 0x600, MODE_ABORT,
- 8, 8, 0, 0, true, true, false, EC_INVALID
+ 8, 8, 0, 0, true, true, false, ExceptionClass::INVALID
);
template<> ArmFault::FaultVals ArmFaultVals<HypervisorTrap>::vals(
// @todo: double check these values
"Hypervisor Trap", 0x014, 0x000, 0x200, 0x400, 0x600, MODE_HYP,
- 0, 0, 0, 0, false, false, false, EC_UNKNOWN
+ 0, 0, 0, 0, false, false, false, ExceptionClass::UNKNOWN
);
template<> ArmFault::FaultVals ArmFaultVals<SecureMonitorTrap>::vals(
"Secure Monitor Trap", 0x004, 0x000, 0x200, 0x400, 0x600, MODE_MON,
- 4, 2, 0, 0, false, false, false, EC_UNKNOWN
+ 4, 2, 0, 0, false, false, false, ExceptionClass::UNKNOWN
);
template<> ArmFault::FaultVals ArmFaultVals<Interrupt>::vals(
"IRQ", 0x018, 0x080, 0x280, 0x480, 0x680, MODE_IRQ,
- 4, 4, 0, 0, false, true, false, EC_UNKNOWN
+ 4, 4, 0, 0, false, true, false, ExceptionClass::UNKNOWN
);
template<> ArmFault::FaultVals ArmFaultVals<VirtualInterrupt>::vals(
"Virtual IRQ", 0x018, 0x080, 0x280, 0x480, 0x680, MODE_IRQ,
- 4, 4, 0, 0, false, true, false, EC_INVALID
+ 4, 4, 0, 0, false, true, false, ExceptionClass::INVALID
);
template<> ArmFault::FaultVals ArmFaultVals<FastInterrupt>::vals(
"FIQ", 0x01C, 0x100, 0x300, 0x500, 0x700, MODE_FIQ,
- 4, 4, 0, 0, false, true, true, EC_UNKNOWN
+ 4, 4, 0, 0, false, true, true, ExceptionClass::UNKNOWN
);
template<> ArmFault::FaultVals ArmFaultVals<VirtualFastInterrupt>::vals(
"Virtual FIQ", 0x01C, 0x100, 0x300, 0x500, 0x700, MODE_FIQ,
- 4, 4, 0, 0, false, true, true, EC_INVALID
+ 4, 4, 0, 0, false, true, true, ExceptionClass::INVALID
);
template<> ArmFault::FaultVals ArmFaultVals<IllegalInstSetStateFault>::vals(
"Illegal Inst Set State Fault", 0x004, 0x000, 0x200, 0x400, 0x600, MODE_UNDEFINED,
- 4, 2, 0, 0, true, false, false, EC_ILLEGAL_INST
+ 4, 2, 0, 0, true, false, false, ExceptionClass::ILLEGAL_INST
);
template<> ArmFault::FaultVals ArmFaultVals<SupervisorTrap>::vals(
// Some dummy values (SupervisorTrap is AArch64-only)
"Supervisor Trap", 0x014, 0x000, 0x200, 0x400, 0x600, MODE_SVC,
- 0, 0, 0, 0, false, false, false, EC_UNKNOWN
+ 0, 0, 0, 0, false, false, false, ExceptionClass::UNKNOWN
);
template<> ArmFault::FaultVals ArmFaultVals<PCAlignmentFault>::vals(
// Some dummy values (PCAlignmentFault is AArch64-only)
"PC Alignment Fault", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC,
- 0, 0, 0, 0, true, false, false, EC_PC_ALIGNMENT
+ 0, 0, 0, 0, true, false, false, ExceptionClass::PC_ALIGNMENT
);
template<> ArmFault::FaultVals ArmFaultVals<SPAlignmentFault>::vals(
// Some dummy values (SPAlignmentFault is AArch64-only)
"SP Alignment Fault", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC,
- 0, 0, 0, 0, true, false, false, EC_STACK_PTR_ALIGNMENT
+ 0, 0, 0, 0, true, false, false, ExceptionClass::STACK_PTR_ALIGNMENT
);
template<> ArmFault::FaultVals ArmFaultVals<SystemError>::vals(
// Some dummy values (SError is AArch64-only)
"SError", 0x000, 0x180, 0x380, 0x580, 0x780, MODE_SVC,
- 0, 0, 0, 0, false, true, true, EC_SERROR
+ 0, 0, 0, 0, false, true, true, ExceptionClass::SERROR
);
template<> ArmFault::FaultVals ArmFaultVals<SoftwareBreakpoint>::vals(
// Some dummy values (SoftwareBreakpoint is AArch64-only)
"Software Breakpoint", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC,
- 0, 0, 0, 0, true, false, false, EC_SOFTWARE_BREAKPOINT
+ 0, 0, 0, 0, true, false, false, ExceptionClass::SOFTWARE_BREAKPOINT
);
template<> ArmFault::FaultVals ArmFaultVals<HardwareBreakpoint>::vals(
"Hardware Breakpoint", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC,
- 0, 0, 0, 0, true, false, false, EC_HW_BREAKPOINT
+ 0, 0, 0, 0, true, false, false, ExceptionClass::HW_BREAKPOINT
);
template<> ArmFault::FaultVals ArmFaultVals<Watchpoint>::vals(
"Watchpoint", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC,
- 0, 0, 0, 0, true, false, false, EC_WATCHPOINT
+ 0, 0, 0, 0, true, false, false, ExceptionClass::WATCHPOINT
);
template<> ArmFault::FaultVals ArmFaultVals<SoftwareStepFault>::vals(
"SoftwareStep", 0x000, 0x000, 0x200, 0x400, 0x600, MODE_SVC,
- 0, 0, 0, 0, true, false, false, EC_SOFTWARE_STEP
+ 0, 0, 0, 0, true, false, false, ExceptionClass::SOFTWARE_STEP
);
template<> ArmFault::FaultVals ArmFaultVals<ArmSev>::vals(
// Some dummy values
"ArmSev Flush", 0x000, 0x000, 0x000, 0x000, 0x000, MODE_SVC,
- 0, 0, 0, 0, false, true, true, EC_UNKNOWN
+ 0, 0, 0, 0, false, true, true, ExceptionClass::UNKNOWN
);
Addr
@@ -605,7 +605,7 @@
break;
case MODE_UNDEFINED:
tc->setMiscReg(MISCREG_SPSR_UND, saved_cpsr);
- if (ec(tc) != EC_UNKNOWN)
+ if (ec(tc) != ExceptionClass::UNKNOWN)
setSyndrome(tc, MISCREG_HSR);
break;
case MODE_HYP:
@@ -841,7 +841,7 @@
return 0;
}
- if (overrideEc == EC_INVALID)
+ if (overrideEc == ExceptionClass::INVALID)
return issRaw;
uint32_t new_iss = 0;
@@ -891,8 +891,8 @@
ExceptionClass
SupervisorCall::ec(ThreadContext *tc) const
{
- return (overrideEc != EC_INVALID) ? overrideEc :
- (from64 ? EC_SVC_64 : vals.ec);
+ return (overrideEc != ExceptionClass::INVALID) ? overrideEc :
+ (from64 ? ExceptionClass::SVC_64 : vals.ec);
}
uint32_t
@@ -917,9 +917,9 @@
// If UndefinedInstruction is routed to hypervisor,
// HSR.EC field is 0.
if (hypRouted)
- return EC_UNKNOWN;
+ return ExceptionClass::UNKNOWN;
else
- return (overrideEc != EC_INVALID) ? overrideEc : vals.ec;
+ return (overrideEc != ExceptionClass::INVALID) ? overrideEc : vals.ec;
}
@@ -944,13 +944,13 @@
ExceptionClass
HypervisorCall::ec(ThreadContext *tc) const
{
- return from64 ? EC_HVC_64 : vals.ec;
+ return from64 ? ExceptionClass::HVC_64 : vals.ec;
}
ExceptionClass
HypervisorTrap::ec(ThreadContext *tc) const
{
- return (overrideEc != EC_INVALID) ? overrideEc : vals.ec;
+ return (overrideEc != ExceptionClass::INVALID) ? overrideEc : vals.ec;
}
template<class T>
@@ -1027,7 +1027,7 @@
ExceptionClass
SecureMonitorCall::ec(ThreadContext *tc) const
{
- return (from64 ? EC_SMC_64 : vals.ec);
+ return (from64 ? ExceptionClass::SMC_64 : vals.ec);
}
bool
@@ -1051,16 +1051,16 @@
SupervisorTrap::ec(ThreadContext *tc) const
{
if (hypRouted)
- return EC_UNKNOWN;
+ return ExceptionClass::UNKNOWN;
else
- return (overrideEc != EC_INVALID) ? overrideEc : vals.ec;
+ return (overrideEc != ExceptionClass::INVALID) ? overrideEc : vals.ec;
}
ExceptionClass
SecureMonitorTrap::ec(ThreadContext *tc) const
{
- return (overrideEc != EC_INVALID) ? overrideEc :
- (from64 ? EC_SMC_64 : vals.ec);
+ return (overrideEc != ExceptionClass::INVALID) ? overrideEc :
+ (from64 ? ExceptionClass::SMC_64 : vals.ec);
}
template<class T>
@@ -1268,9 +1268,9 @@
if (to64) {
// AArch64
if (toEL == fromEL)
- return EC_PREFETCH_ABORT_CURR_EL;
+ return ExceptionClass::PREFETCH_ABORT_CURR_EL;
else
- return EC_PREFETCH_ABORT_LOWER_EL;
+ return ExceptionClass::PREFETCH_ABORT_LOWER_EL;
} else {
// AArch32
// Abort faults have different EC codes depending on whether
@@ -1336,9 +1336,9 @@
"SystemErrors (SErrors)!");
}
if (toEL == fromEL)
- return EC_DATA_ABORT_CURR_EL;
+ return ExceptionClass::DATA_ABORT_CURR_EL;
else
- return EC_DATA_ABORT_LOWER_EL;
+ return ExceptionClass::DATA_ABORT_LOWER_EL;
} else {
// AArch32
// Abort faults have different EC codes depending on whether
@@ -1625,7 +1625,7 @@
ExceptionClass
SoftwareBreakpoint::ec(ThreadContext *tc) const
{
- return from64 ? EC_SOFTWARE_BREAKPOINT_64 : vals.ec;
+ return from64 ? ExceptionClass::SOFTWARE_BREAKPOINT_64 : vals.ec;
}
HardwareBreakpoint::HardwareBreakpoint(Addr vaddr, uint32_t _iss)
@@ -1646,9 +1646,9 @@
{
// AArch64
if (toEL == fromEL)
- return EC_HW_BREAKPOINT_CURR_EL;
+ return ExceptionClass::HW_BREAKPOINT_CURR_EL;
else
- return EC_HW_BREAKPOINT_LOWER_EL;
+ return ExceptionClass::HW_BREAKPOINT_LOWER_EL;
}
void
@@ -1734,9 +1734,9 @@
{
// AArch64
if (toEL == fromEL)
- return EC_WATCHPOINT_CURR_EL;
+ return ExceptionClass::WATCHPOINT_CURR_EL;
else
- return EC_WATCHPOINT_LOWER_EL;
+ return ExceptionClass::WATCHPOINT_LOWER_EL;
}
SoftwareStepFault::SoftwareStepFault(ExtMachInst mach_inst, bool is_ldx,
@@ -1762,9 +1762,9 @@
{
// AArch64
if (toEL == fromEL)
- return EC_SOFTWARE_STEP_CURR_EL;
+ return ExceptionClass::SOFTWARE_STEP_CURR_EL;
else
- return EC_SOFTWARE_STEP_LOWER_EL;
+ return ExceptionClass::SOFTWARE_STEP_LOWER_EL;
}
uint32_t
diff --git a/src/arch/arm/faults.hh b/src/arch/arm/faults.hh
index 6c0cda6..ec60d62 100644
--- a/src/arch/arm/faults.hh
+++ b/src/arch/arm/faults.hh
@@ -306,7 +306,8 @@
il(ThreadContext *tc) const override
{
// ESR.IL = 1 if exception cause is unknown (EC = 0)
- return ec(tc) == EC_UNKNOWN || !machInst.thumb || machInst.bigThumb;
+ return ec(tc) == ExceptionClass::UNKNOWN ||
+ !machInst.thumb || machInst.bigThumb;
}
uint32_t iss() const override { return issRaw; }
};
@@ -336,7 +337,7 @@
bool _disabled = false) :
ArmFaultVals<UndefinedInstruction>(mach_inst),
unknown(_unknown), disabled(_disabled),
- overrideEc(EC_INVALID), mnemonic(_mnemonic)
+ overrideEc(ExceptionClass::INVALID), mnemonic(_mnemonic)
{}
UndefinedInstruction(ExtMachInst mach_inst, uint32_t _iss,
ExceptionClass _overrideEc, const char *_mnemonic = NULL) :
@@ -361,7 +362,7 @@
ExceptionClass overrideEc;
public:
SupervisorCall(ExtMachInst mach_inst, uint32_t _iss,
- ExceptionClass _overrideEc = EC_INVALID) :
+ ExceptionClass _overrideEc = ExceptionClass::INVALID) :
ArmFaultVals<SupervisorCall>(mach_inst, _iss),
overrideEc(_overrideEc)
{
@@ -404,7 +405,7 @@
public:
SupervisorTrap(ExtMachInst mach_inst, uint32_t _iss,
- ExceptionClass _overrideEc = EC_INVALID) :
+ ExceptionClass _overrideEc = ExceptionClass::INVALID) :
ArmFaultVals<SupervisorTrap>(mach_inst, _iss),
overrideEc(_overrideEc)
{}
@@ -424,7 +425,7 @@
public:
SecureMonitorTrap(ExtMachInst mach_inst, uint32_t _iss,
- ExceptionClass _overrideEc = EC_INVALID) :
+ ExceptionClass _overrideEc = ExceptionClass::INVALID) :
ArmFaultVals<SecureMonitorTrap>(mach_inst, _iss),
overrideEc(_overrideEc)
{}
@@ -454,7 +455,7 @@
public:
HypervisorTrap(ExtMachInst mach_inst, uint32_t _iss,
- ExceptionClass _overrideEc = EC_INVALID) :
+ ExceptionClass _overrideEc = ExceptionClass::INVALID) :
ArmFaultVals<HypervisorTrap>(mach_inst, _iss),
overrideEc(_overrideEc)
{}
diff --git a/src/arch/arm/insts/misc64.cc b/src/arch/arm/insts/misc64.cc
index 58d6bd3..0fde077 100644
--- a/src/arch/arm/insts/misc64.cc
+++ b/src/arch/arm/insts/misc64.cc
@@ -104,7 +104,7 @@
Fault
MiscRegOp64::generateTrap(ExceptionLevel el) const
{
- return generateTrap(el, EC_TRAPPED_MSR_MRS_64, iss());
+ return generateTrap(el, ExceptionClass::TRAPPED_MSR_MRS_64, iss());
}
Fault
diff --git a/src/arch/arm/insts/static_inst.cc b/src/arch/arm/insts/static_inst.cc
index ba0e1cf..c07fb39 100644
--- a/src/arch/arm/insts/static_inst.cc
+++ b/src/arch/arm/insts/static_inst.cc
@@ -656,14 +656,14 @@
{
switch (el) {
case EL1:
- return std::make_shared<SupervisorTrap>(machInst, 0x1E00000,
- EC_TRAPPED_SIMD_FP);
+ return std::make_shared<SupervisorTrap>(
+ machInst, 0x1E00000, ExceptionClass::TRAPPED_SIMD_FP);
case EL2:
- return std::make_shared<HypervisorTrap>(machInst, 0x1E00000,
- EC_TRAPPED_SIMD_FP);
+ return std::make_shared<HypervisorTrap>(
+ machInst, 0x1E00000, ExceptionClass::TRAPPED_SIMD_FP);
case EL3:
- return std::make_shared<SecureMonitorTrap>(machInst, 0x1E00000,
- EC_TRAPPED_SIMD_FP);
+ return std::make_shared<SecureMonitorTrap>(
+ machInst, 0x1E00000, ExceptionClass::TRAPPED_SIMD_FP);
default:
panic("Illegal EL in advSIMDFPAccessTrap64\n");
@@ -781,11 +781,11 @@
if (cur_el == EL2) {
return std::make_shared<UndefinedInstruction>(
machInst, iss,
- EC_TRAPPED_HCPTR, mnemonic);
+ ExceptionClass::TRAPPED_HCPTR, mnemonic);
} else {
return std::make_shared<HypervisorTrap>(
machInst, iss,
- EC_TRAPPED_HCPTR);
+ ExceptionClass::TRAPPED_HCPTR);
}
}
@@ -852,13 +852,15 @@
case EL1:
return std::make_shared<UndefinedInstruction>(
machInst, iss,
- EC_TRAPPED_WFI_WFE, mnemonic);
+ ExceptionClass::TRAPPED_WFI_WFE, mnemonic);
case EL2:
- return std::make_shared<HypervisorTrap>(machInst, iss,
- EC_TRAPPED_WFI_WFE);
+ return std::make_shared<HypervisorTrap>(
+ machInst, iss,
+ ExceptionClass::TRAPPED_WFI_WFE);
case EL3:
- return std::make_shared<SecureMonitorTrap>(machInst, iss,
- EC_TRAPPED_WFI_WFE);
+ return std::make_shared<SecureMonitorTrap>(
+ machInst, iss,
+ ExceptionClass::TRAPPED_WFI_WFE);
default:
panic("Unrecognized Exception Level: %d\n", targetEL);
}
@@ -883,14 +885,17 @@
0x1E00000; /* WFI Instruction syndrome */
switch (targetEL) {
case EL1:
- return std::make_shared<SupervisorTrap>(machInst, iss,
- EC_TRAPPED_WFI_WFE);
+ return std::make_shared<SupervisorTrap>(
+ machInst, iss,
+ ExceptionClass::TRAPPED_WFI_WFE);
case EL2:
- return std::make_shared<HypervisorTrap>(machInst, iss,
- EC_TRAPPED_WFI_WFE);
+ return std::make_shared<HypervisorTrap>(
+ machInst, iss,
+ ExceptionClass::TRAPPED_WFI_WFE);
case EL3:
- return std::make_shared<SecureMonitorTrap>(machInst, iss,
- EC_TRAPPED_WFI_WFE);
+ return std::make_shared<SecureMonitorTrap>(
+ machInst, iss,
+ ExceptionClass::TRAPPED_WFI_WFE);
default:
panic("Unrecognized Exception Level: %d\n", targetEL);
}
@@ -972,7 +977,7 @@
// ArmFault class.
return std::make_shared<UndefinedInstruction>(
machInst, 0,
- EC_UNKNOWN, mnemonic);
+ ExceptionClass::UNKNOWN, mnemonic);
}
}
@@ -983,11 +988,14 @@
switch (pstateEL) {
case EL0:
case EL1:
- return std::make_shared<SupervisorTrap>(machInst, 0, EC_UNKNOWN);
+ return std::make_shared<SupervisorTrap>(
+ machInst, 0, ExceptionClass::UNKNOWN);
case EL2:
- return std::make_shared<HypervisorTrap>(machInst, 0, EC_UNKNOWN);
+ return std::make_shared<HypervisorTrap>(
+ machInst, 0, ExceptionClass::UNKNOWN);
case EL3:
- return std::make_shared<SecureMonitorTrap>(machInst, 0, EC_UNKNOWN);
+ return std::make_shared<SecureMonitorTrap>(
+ machInst, 0, ExceptionClass::UNKNOWN);
default:
panic("Unrecognized Exception Level: %d\n", pstateEL);
break;
@@ -1001,12 +1009,14 @@
{
switch (el) {
case EL1:
- return std::make_shared<SupervisorTrap>(machInst, 0, EC_TRAPPED_SVE);
+ return std::make_shared<SupervisorTrap>(
+ machInst, 0, ExceptionClass::TRAPPED_SVE);
case EL2:
- return std::make_shared<HypervisorTrap>(machInst, 0, EC_TRAPPED_SVE);
+ return std::make_shared<HypervisorTrap>(
+ machInst, 0, ExceptionClass::TRAPPED_SVE);
case EL3:
- return std::make_shared<SecureMonitorTrap>(machInst, 0,
- EC_TRAPPED_SVE);
+ return std::make_shared<SecureMonitorTrap>(
+ machInst, 0, ExceptionClass::TRAPPED_SVE);
default:
panic("Illegal EL in sveAccessTrap\n");
diff --git a/src/arch/arm/isa/insts/branch.isa b/src/arch/arm/isa/insts/branch.isa
index c14e1f8..23ec1e1 100644
--- a/src/arch/arm/isa/insts/branch.isa
+++ b/src/arch/arm/isa/insts/branch.isa
@@ -153,7 +153,8 @@
if (ArmSystem::haveEL(xc->tcBase(), EL2) && hstr.tjdbx &&
!isSecure(xc->tcBase()) && (cpsr.mode != MODE_HYP)) {
- fault = std::make_shared<HypervisorTrap>(machInst, op1, EC_TRAPPED_BXJ);
+ fault = std::make_shared<HypervisorTrap>(
+ machInst, op1, ExceptionClass::TRAPPED_BXJ);
}
IWNPC = Op1;
'''
diff --git a/src/arch/arm/isa/insts/fp.isa b/src/arch/arm/isa/insts/fp.isa
index e0df71c..1d54324 100644
--- a/src/arch/arm/isa/insts/fp.isa
+++ b/src/arch/arm/isa/insts/fp.isa
@@ -225,7 +225,7 @@
}
if (hypTrap) {
return std::make_shared<HypervisorTrap>(machInst, imm,
- EC_TRAPPED_CP10_MRC_VMRS);
+ ExceptionClass::TRAPPED_CP10_MRC_VMRS);
}
}
Dest = MiscOp1;
diff --git a/src/arch/arm/isa/insts/misc.isa b/src/arch/arm/isa/insts/misc.isa
index 96c0d63..bfcb693 100644
--- a/src/arch/arm/isa/insts/misc.isa
+++ b/src/arch/arm/isa/insts/misc.isa
@@ -96,8 +96,9 @@
if ((cpsr.mode != MODE_USER) && FullSystem) {
if (EL2Enabled(xc->tcBase()) && (cpsr.mode != MODE_HYP) && hcr.tsc) {
- fault = std::make_shared<HypervisorTrap>(machInst, 0,
- EC_SMC_TO_HYP);
+ fault = std::make_shared<HypervisorTrap>(
+ machInst, 0,
+ ExceptionClass::SMC_TO_HYP);
} else {
if (scr.scd) {
fault = disabledFault();
@@ -898,8 +899,9 @@
mnemonic);
}
if (mcrMrc14TrapToHyp((MiscRegIndex) op1, xc->tcBase(), imm)) {
- return std::make_shared<HypervisorTrap>(machInst, imm,
- EC_TRAPPED_CP14_MCR_MRC);
+ return std::make_shared<HypervisorTrap>(
+ machInst, imm,
+ ExceptionClass::TRAPPED_CP14_MCR_MRC);
}
Dest = MiscOp1;
'''
@@ -922,8 +924,9 @@
mnemonic);
}
if (mcrMrc14TrapToHyp(miscReg, xc->tcBase(), imm)) {
- return std::make_shared<HypervisorTrap>(machInst, imm,
- EC_TRAPPED_CP14_MCR_MRC);
+ return std::make_shared<HypervisorTrap>(
+ machInst, imm,
+ ExceptionClass::TRAPPED_CP14_MCR_MRC);
}
MiscDest = Op1;
'''
@@ -1197,7 +1200,7 @@
if ((imm != 0) && mcrMrc15TrapToHyp(MISCREG_CP15ISB,
xc->tcBase(), imm)) {
return std::make_shared<HypervisorTrap>(machInst, imm,
- EC_TRAPPED_CP15_MCR_MRC);
+ ExceptionClass::TRAPPED_CP15_MCR_MRC);
}
'''
isbIop = ArmInstObjParams("isb", "Isb", "ImmOp",
@@ -1213,7 +1216,7 @@
if ((imm != 0) && mcrMrc15TrapToHyp(MISCREG_CP15DSB,
xc->tcBase(), imm)) {
return std::make_shared<HypervisorTrap>(machInst, imm,
- EC_TRAPPED_CP15_MCR_MRC);
+ ExceptionClass::TRAPPED_CP15_MCR_MRC);
}
'''
dsbIop = ArmInstObjParams("dsb", "Dsb", "ImmOp",
@@ -1230,7 +1233,7 @@
if ((imm != 0) && mcrMrc15TrapToHyp(MISCREG_CP15DMB,
xc->tcBase(), imm)) {
return std::make_shared<HypervisorTrap>(machInst, imm,
- EC_TRAPPED_CP15_MCR_MRC);
+ ExceptionClass::TRAPPED_CP15_MCR_MRC);
}
'''
dmbIop = ArmInstObjParams("dmb", "Dmb", "ImmOp",
diff --git a/src/arch/arm/pauth_helpers.cc b/src/arch/arm/pauth_helpers.cc
index 7b3270c..3e8f18e 100644
--- a/src/arch/arm/pauth_helpers.cc
+++ b/src/arch/arm/pauth_helpers.cc
@@ -121,9 +121,11 @@
switch (target_el) {
case EL2:
- return std::make_shared<HypervisorTrap>(0x0, 0, EC_TRAPPED_PAC);
+ return std::make_shared<HypervisorTrap>(
+ 0x0, 0, ExceptionClass::TRAPPED_PAC);
case EL3:
- return std::make_shared<SecureMonitorTrap>(0x0, 0, EC_TRAPPED_PAC);
+ return std::make_shared<SecureMonitorTrap>(
+ 0x0, 0, ExceptionClass::TRAPPED_PAC);
default:
return NoFault;
}
diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc
index 12ac831..6b62e21 100644
--- a/src/arch/arm/regs/misc.cc
+++ b/src/arch/arm/regs/misc.cc
@@ -1311,18 +1311,23 @@
const bool in_host = hcr.e2h && hcr.tge;
if (!(el2_enabled && in_host) && cpacr.fpen != 0b11) {
if (el2_enabled && hcr.tge) {
- return inst.generateTrap(EL2, EC_UNKNOWN, inst.iss());
+ return inst.generateTrap(EL2, ExceptionClass::UNKNOWN, inst.iss());
} else {
- return inst.generateTrap(EL1, EC_TRAPPED_SIMD_FP, 0x1E00000);
+ return inst.generateTrap(EL1,
+ ExceptionClass::TRAPPED_SIMD_FP, 0x1E00000);
}
} else if (el2_enabled && in_host && cptr_el2.fpen != 0b11) {
- return inst.generateTrap(EL2, EC_TRAPPED_SIMD_FP, 0x1E00000);
+ return inst.generateTrap(EL2,
+ ExceptionClass::TRAPPED_SIMD_FP, 0x1E00000);
} else if (el2_enabled && hcr.e2h && ((cptr_el2.fpen & 0b1) == 0b0)) {
- return inst.generateTrap(EL2, EC_TRAPPED_SIMD_FP, 0x1E00000);
+ return inst.generateTrap(EL2,
+ ExceptionClass::TRAPPED_SIMD_FP, 0x1E00000);
} else if (el2_enabled && !hcr.e2h && cptr_el2.tfp) {
- return inst.generateTrap(EL2, EC_TRAPPED_SIMD_FP, 0x1E00000);
+ return inst.generateTrap(EL2,
+ ExceptionClass::TRAPPED_SIMD_FP, 0x1E00000);
} else if (ArmSystem::haveEL(tc, EL3) && cptr_el3.tfp) {
- return inst.generateTrap(EL3, EC_TRAPPED_SIMD_FP, 0x1E00000);
+ return inst.generateTrap(EL3,
+ ExceptionClass::TRAPPED_SIMD_FP, 0x1E00000);
} else {
return NoFault;
}
@@ -1339,13 +1344,17 @@
const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
const bool el2_enabled = EL2Enabled(tc);
if ((cpacr.fpen & 0b1) == 0b0) {
- return inst.generateTrap(EL1, EC_TRAPPED_SIMD_FP, 0x1E00000);
+ return inst.generateTrap(EL1,
+ ExceptionClass::TRAPPED_SIMD_FP, 0x1E00000);
} else if (el2_enabled && !hcr.e2h && cptr_el2.tfp) {
- return inst.generateTrap(EL2, EC_TRAPPED_SIMD_FP, 0x1E00000);
+ return inst.generateTrap(EL2,
+ ExceptionClass::TRAPPED_SIMD_FP, 0x1E00000);
} else if (el2_enabled && hcr.e2h && ((cptr_el2.fpen & 0b1) == 0b0)) {
- return inst.generateTrap(EL2, EC_TRAPPED_SIMD_FP, 0x1E00000);
+ return inst.generateTrap(EL2,
+ ExceptionClass::TRAPPED_SIMD_FP, 0x1E00000);
} else if (ArmSystem::haveEL(tc, EL3) && cptr_el3.tfp) {
- return inst.generateTrap(EL3, EC_TRAPPED_SIMD_FP, 0x1E00000);
+ return inst.generateTrap(EL3,
+ ExceptionClass::TRAPPED_SIMD_FP, 0x1E00000);
} else {
return NoFault;
}
@@ -1360,11 +1369,14 @@
const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
if (!hcr.e2h && cptr_el2.tfp) {
- return inst.generateTrap(EL2, EC_TRAPPED_SIMD_FP, 0x1E00000);
+ return inst.generateTrap(EL2,
+ ExceptionClass::TRAPPED_SIMD_FP, 0x1E00000);
} else if (hcr.e2h && ((cptr_el2.fpen & 0b1) == 0b0)) {
- return inst.generateTrap(EL2, EC_TRAPPED_SIMD_FP, 0x1E00000);
+ return inst.generateTrap(EL2,
+ ExceptionClass::TRAPPED_SIMD_FP, 0x1E00000);
} else if (ArmSystem::haveEL(tc, EL3) && cptr_el3.tfp) {
- return inst.generateTrap(EL3, EC_TRAPPED_SIMD_FP, 0x1E00000);
+ return inst.generateTrap(EL3,
+ ExceptionClass::TRAPPED_SIMD_FP, 0x1E00000);
} else {
return NoFault;
}
@@ -1376,7 +1388,8 @@
{
const CPTR cptr_el3 = tc->readMiscReg(MISCREG_CPTR_EL3);
if (cptr_el3.tfp) {
- return inst.generateTrap(EL3, EC_TRAPPED_SIMD_FP, 0x1E00000);
+ return inst.generateTrap(EL3,
+ ExceptionClass::TRAPPED_SIMD_FP, 0x1E00000);
} else {
return NoFault;
}
@@ -1562,13 +1575,13 @@
const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
const bool el2_enabled = EL2Enabled(tc);
if (!(cpacr_el1.zen & 0x1)) {
- return inst.generateTrap(EL1, EC_TRAPPED_SVE, 0);
+ return inst.generateTrap(EL1, ExceptionClass::TRAPPED_SVE, 0);
} else if (el2_enabled && !hcr.e2h && cptr_el2.tz) {
- return inst.generateTrap(EL2, EC_TRAPPED_SVE, 0);
+ return inst.generateTrap(EL2, ExceptionClass::TRAPPED_SVE, 0);
} else if (el2_enabled && hcr.e2h && !(cptr_el2.zen & 0x1)) {
- return inst.generateTrap(EL2, EC_TRAPPED_SVE, 0);
+ return inst.generateTrap(EL2, ExceptionClass::TRAPPED_SVE, 0);
} else if (ArmSystem::haveEL(tc, EL3) && !cptr_el3.ez) {
- return inst.generateTrap(EL3, EC_TRAPPED_SVE, 0);
+ return inst.generateTrap(EL3, ExceptionClass::TRAPPED_SVE, 0);
} else {
return NoFault;
}
@@ -1583,11 +1596,11 @@
const HCR hcr = tc->readMiscReg(MISCREG_HCR_EL2);
if (!hcr.e2h && cptr_el2.tz) {
- return inst.generateTrap(EL2, EC_TRAPPED_SVE, 0);
+ return inst.generateTrap(EL2, ExceptionClass::TRAPPED_SVE, 0);
} else if (hcr.e2h && !(cptr_el2.zen & 0x1)) {
- return inst.generateTrap(EL2, EC_TRAPPED_SVE, 0);
+ return inst.generateTrap(EL2, ExceptionClass::TRAPPED_SVE, 0);
} else if (ArmSystem::haveEL(tc, EL3) && !cptr_el3.ez) {
- return inst.generateTrap(EL3, EC_TRAPPED_SVE, 0);
+ return inst.generateTrap(EL3, ExceptionClass::TRAPPED_SVE, 0);
} else {
return NoFault;
}
@@ -1599,7 +1612,7 @@
{
const CPTR cptr_el3 = tc->readMiscReg(MISCREG_CPTR_EL3);
if (!cptr_el3.ez) {
- return inst.generateTrap(EL3, EC_TRAPPED_SVE, 0);
+ return inst.generateTrap(EL3, ExceptionClass::TRAPPED_SVE, 0);
} else {
return NoFault;
}
diff --git a/src/arch/arm/self_debug.cc b/src/arch/arm/self_debug.cc
index 85fbabe..27064cd 100644
--- a/src/arch/arm/self_debug.cc
+++ b/src/arch/arm/self_debug.cc
@@ -725,7 +725,7 @@
if (do_debug) {
if (enableTdeTge) {
return std::make_shared<HypervisorTrap>(0, 0x22,
- EC_PREFETCH_ABORT_TO_HYP);
+ ExceptionClass::PREFETCH_ABORT_TO_HYP);
} else {
return std::make_shared<PrefetchAbort>(addr,
ArmFault::DebugEvent, false,
diff --git a/src/arch/arm/types.hh b/src/arch/arm/types.hh
index 734fe6f..44b2047 100644
--- a/src/arch/arm/types.hh
+++ b/src/arch/arm/types.hh
@@ -297,57 +297,57 @@
MODE_MAXMODE = MODE_SYSTEM
};
- enum ExceptionClass
+ enum class ExceptionClass
{
- EC_INVALID = -1,
- EC_UNKNOWN = 0x0,
- EC_TRAPPED_WFI_WFE = 0x1,
- EC_TRAPPED_CP15_MCR_MRC = 0x3,
- EC_TRAPPED_CP15_MCRR_MRRC = 0x4,
- EC_TRAPPED_CP14_MCR_MRC = 0x5,
- EC_TRAPPED_CP14_LDC_STC = 0x6,
- EC_TRAPPED_HCPTR = 0x7,
- EC_TRAPPED_SIMD_FP = 0x7, // AArch64 alias
- EC_TRAPPED_CP10_MRC_VMRS = 0x8,
- EC_TRAPPED_PAC = 0x9,
- EC_TRAPPED_BXJ = 0xA,
- EC_TRAPPED_CP14_MCRR_MRRC = 0xC,
- EC_ILLEGAL_INST = 0xE,
- EC_SVC_TO_HYP = 0x11,
- EC_SVC = 0x11, // AArch64 alias
- EC_HVC = 0x12,
- EC_SMC_TO_HYP = 0x13,
- EC_SMC = 0x13, // AArch64 alias
- EC_SVC_64 = 0x15,
- EC_HVC_64 = 0x16,
- EC_SMC_64 = 0x17,
- EC_TRAPPED_MSR_MRS_64 = 0x18,
- EC_TRAPPED_SVE = 0x19,
- EC_PREFETCH_ABORT_TO_HYP = 0x20,
- EC_PREFETCH_ABORT_LOWER_EL = 0x20, // AArch64 alias
- EC_PREFETCH_ABORT_FROM_HYP = 0x21,
- EC_PREFETCH_ABORT_CURR_EL = 0x21, // AArch64 alias
- EC_PC_ALIGNMENT = 0x22,
- EC_DATA_ABORT_TO_HYP = 0x24,
- EC_DATA_ABORT_LOWER_EL = 0x24, // AArch64 alias
- EC_DATA_ABORT_FROM_HYP = 0x25,
- EC_DATA_ABORT_CURR_EL = 0x25, // AArch64 alias
- EC_STACK_PTR_ALIGNMENT = 0x26,
- EC_FP_EXCEPTION = 0x28,
- EC_FP_EXCEPTION_64 = 0x2C,
- EC_SERROR = 0x2F,
- EC_HW_BREAKPOINT = 0x30,
- EC_HW_BREAKPOINT_LOWER_EL = 0x30,
- EC_HW_BREAKPOINT_CURR_EL = 0x31,
- EC_SOFTWARE_STEP = 0x32,
- EC_SOFTWARE_STEP_LOWER_EL = 0x32,
- EC_SOFTWARE_STEP_CURR_EL = 0x33,
- EC_WATCHPOINT = 0x34,
- EC_WATCHPOINT_LOWER_EL = 0x34,
- EC_WATCHPOINT_CURR_EL = 0x35,
- EC_SOFTWARE_BREAKPOINT = 0x38,
- EC_VECTOR_CATCH = 0x3A,
- EC_SOFTWARE_BREAKPOINT_64 = 0x3C,
+ INVALID = -1,
+ UNKNOWN = 0x0,
+ TRAPPED_WFI_WFE = 0x1,
+ TRAPPED_CP15_MCR_MRC = 0x3,
+ TRAPPED_CP15_MCRR_MRRC = 0x4,
+ TRAPPED_CP14_MCR_MRC = 0x5,
+ TRAPPED_CP14_LDC_STC = 0x6,
+ TRAPPED_HCPTR = 0x7,
+ TRAPPED_SIMD_FP = 0x7, // AArch64 alias
+ TRAPPED_CP10_MRC_VMRS = 0x8,
+ TRAPPED_PAC = 0x9,
+ TRAPPED_BXJ = 0xA,
+ TRAPPED_CP14_MCRR_MRRC = 0xC,
+ ILLEGAL_INST = 0xE,
+ SVC_TO_HYP = 0x11,
+ SVC = 0x11, // AArch64 alias
+ HVC = 0x12,
+ SMC_TO_HYP = 0x13,
+ SMC = 0x13, // AArch64 alias
+ SVC_64 = 0x15,
+ HVC_64 = 0x16,
+ SMC_64 = 0x17,
+ TRAPPED_MSR_MRS_64 = 0x18,
+ TRAPPED_SVE = 0x19,
+ PREFETCH_ABORT_TO_HYP = 0x20,
+ PREFETCH_ABORT_LOWER_EL = 0x20, // AArch64 alias
+ PREFETCH_ABORT_FROM_HYP = 0x21,
+ PREFETCH_ABORT_CURR_EL = 0x21, // AArch64 alias
+ PC_ALIGNMENT = 0x22,
+ DATA_ABORT_TO_HYP = 0x24,
+ DATA_ABORT_LOWER_EL = 0x24, // AArch64 alias
+ DATA_ABORT_FROM_HYP = 0x25,
+ DATA_ABORT_CURR_EL = 0x25, // AArch64 alias
+ STACK_PTR_ALIGNMENT = 0x26,
+ FP_EXCEPTION = 0x28,
+ FP_EXCEPTION_64 = 0x2C,
+ SERROR = 0x2F,
+ HW_BREAKPOINT = 0x30,
+ HW_BREAKPOINT_LOWER_EL = 0x30,
+ HW_BREAKPOINT_CURR_EL = 0x31,
+ SOFTWARE_STEP = 0x32,
+ SOFTWARE_STEP_LOWER_EL = 0x32,
+ SOFTWARE_STEP_CURR_EL = 0x33,
+ WATCHPOINT = 0x34,
+ WATCHPOINT_LOWER_EL = 0x34,
+ WATCHPOINT_CURR_EL = 0x35,
+ SOFTWARE_BREAKPOINT = 0x38,
+ VECTOR_CATCH = 0x3A,
+ SOFTWARE_BREAKPOINT_64 = 0x3C,
};
/**
diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc
index eb2a9f5..e6f4a23 100644
--- a/src/arch/arm/utility.cc
+++ b/src/arch/arm/utility.cc
@@ -502,7 +502,7 @@
mcrMrc15Trap(const MiscRegIndex misc_reg, ExtMachInst mach_inst,
ThreadContext *tc, uint32_t imm)
{
- ExceptionClass ec = EC_TRAPPED_CP15_MCR_MRC;
+ ExceptionClass ec = ExceptionClass::TRAPPED_CP15_MCR_MRC;
if (mcrMrc15TrapToHyp(misc_reg, tc, imm, &ec))
return std::make_shared<HypervisorTrap>(mach_inst, imm, ec);
return AArch64AArch32SystemAccessTrap(misc_reg, mach_inst, tc, imm, ec);
@@ -722,7 +722,7 @@
mcrrMrrc15Trap(const MiscRegIndex misc_reg, ExtMachInst mach_inst,
ThreadContext *tc, uint32_t imm)
{
- ExceptionClass ec = EC_TRAPPED_CP15_MCRR_MRRC;
+ ExceptionClass ec = ExceptionClass::TRAPPED_CP15_MCRR_MRRC;
if (mcrrMrrc15TrapToHyp(misc_reg, tc, imm, &ec))
return std::make_shared<HypervisorTrap>(mach_inst, imm, ec);
return AArch64AArch32SystemAccessTrap(misc_reg, mach_inst, tc, imm, ec);
@@ -852,7 +852,7 @@
// As per the architecture, this hyp trap should have uncategorized
// exception class
if (ec)
- *ec = EC_UNKNOWN;
+ *ec = ExceptionClass::UNKNOWN;
return true;
}
return false;
