arch-arm, dev-arm: MISCREG_ICC_CTLR_EL1 using AA64 banking
Change-Id: Ib1691f1cba08251a36ceb959849b61c33cc3e93b
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20626
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc
index 76a9917..5f45916 100644
--- a/src/arch/arm/miscregs.cc
+++ b/src/arch/arm/miscregs.cc
@@ -4616,7 +4616,7 @@
.secure().exceptUserMode()
.mapsTo(MISCREG_ICC_BPR1_S);
InitReg(MISCREG_ICC_CTLR_EL1)
- .banked()
+ .banked64()
.mapsTo(MISCREG_ICC_CTLR);
InitReg(MISCREG_ICC_CTLR_EL1_NS)
.bankedChild()
diff --git a/src/dev/arm/gic_v3_cpu_interface.cc b/src/dev/arm/gic_v3_cpu_interface.cc
index d3d73a3..786f1ab 100644
--- a/src/dev/arm/gic_v3_cpu_interface.cc
+++ b/src/dev/arm/gic_v3_cpu_interface.cc
@@ -553,6 +553,7 @@
return readMiscReg(MISCREG_ICV_CTLR_EL1);
}
+ value = readBankedMiscReg(MISCREG_ICC_CTLR_EL1);
// Enforce value for RO bits
// ExtRange [19], INTIDs in the range 1024..8191 not supported
// RSS [18], SGIs with affinity level 0 values of 0-255 are supported
@@ -1132,7 +1133,7 @@
*/
ICC_CTLR_EL1 requested_icc_ctlr_el1 = val;
ICC_CTLR_EL1 icc_ctlr_el1 =
- isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1);
+ readBankedMiscReg(MISCREG_ICC_CTLR_EL1);
ICC_CTLR_EL3 icc_ctlr_el3 =
isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL3);
@@ -1190,8 +1191,8 @@
isa->setMiscRegNoEffect(MISCREG_ICC_CTLR_EL3, icc_ctlr_el3);
- val = icc_ctlr_el1;
- break;
+ setBankedMiscReg(MISCREG_ICC_CTLR_EL1, icc_ctlr_el1);
+ return;
}
// Virtual Control Register
@@ -1963,8 +1964,11 @@
isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL3);
return icc_ctlr_el3.EOImode_EL3;
} else {
- ICC_CTLR_EL1 icc_ctlr_el1 =
- isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1);
+ ICC_CTLR_EL1 icc_ctlr_el1 = 0;
+ if (inSecureState())
+ icc_ctlr_el1 = isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_S);
+ else
+ icc_ctlr_el1 = isa->readMiscRegNoEffect(MISCREG_ICC_CTLR_EL1_NS);
return icc_ctlr_el1.EOImode;
}
}