fastmodel: Determine what space to use for breakpoints dynamically.
This was hardcoded as 5, but should be determined based on the memory
space IDs the fast model returns. What we do now is have a specific
override for ARM (perhaps conceptually the A76) which looks for an
address space called "Current" which seems to work well.
It's possible that the appropriate address space for a different model
might have a different number, or even a different name. This may need
to be further specialized/parameterized in those cases.
Change-Id: Ie1ef99675fd9bccab50b7fc7add16b82a93bd60b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22143
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
diff --git a/src/arch/arm/fastmodel/iris/arm/thread_context.cc b/src/arch/arm/fastmodel/iris/arm/thread_context.cc
index 181d268..8a36ce3 100644
--- a/src/arch/arm/fastmodel/iris/arm/thread_context.cc
+++ b/src/arch/arm/fastmodel/iris/arm/thread_context.cc
@@ -145,6 +145,22 @@
return pcState().nextInstAddr();
}
+iris::MemorySpaceId
+ArmThreadContext::getBpSpaceId(Addr pc) const
+{
+ if (bpSpaceId == iris::IRIS_UINT64_MAX) {
+ for (auto &space: memorySpaces) {
+ if (space.canonicalMsn == CurrentMsn) {
+ bpSpaceId = space.spaceId;
+ break;
+ }
+ }
+ panic_if(bpSpaceId == iris::IRIS_UINT64_MAX,
+ "Unable to find address space for breakpoints.");
+ }
+ return bpSpaceId;
+}
+
uint64_t
ArmThreadContext::readIntReg(RegIndex reg_idx) const
{
@@ -882,4 +898,6 @@
{ 28, "V28" }, { 29, "V29" }, { 30, "V30" }, { 31, "V31" }
});
+iris::MemorySpaceId ArmThreadContext::bpSpaceId = iris::IRIS_UINT64_MAX;
+
} // namespace Iris
diff --git a/src/arch/arm/fastmodel/iris/arm/thread_context.hh b/src/arch/arm/fastmodel/iris/arm/thread_context.hh
index 6e28c3b..c7f26e3 100644
--- a/src/arch/arm/fastmodel/iris/arm/thread_context.hh
+++ b/src/arch/arm/fastmodel/iris/arm/thread_context.hh
@@ -44,6 +44,7 @@
static IdxNameMap intReg32IdxNameMap;
static IdxNameMap intReg64IdxNameMap;
static IdxNameMap vecRegIdxNameMap;
+ static iris::MemorySpaceId bpSpaceId;
// Temporary holding places for the vector reg accessors to return.
// These are not updated live, only when requested.
@@ -71,6 +72,8 @@
ResourceIds intReg64Ids;
ResourceIds vecRegIds;
+ iris::MemorySpaceId getBpSpaceId(Addr pc) const override;
+
void setIntReg(RegIndex reg_idx, RegVal val) override;
RegVal readIntReg(RegIndex reg_idx) const override;
TheISA::ISA *
diff --git a/src/arch/arm/fastmodel/iris/thread_context.cc b/src/arch/arm/fastmodel/iris/thread_context.cc
index 8721366..ebcd2b8 100644
--- a/src/arch/arm/fastmodel/iris/thread_context.cc
+++ b/src/arch/arm/fastmodel/iris/thread_context.cc
@@ -134,8 +134,9 @@
ThreadContext::installBp(BpInfoIt it)
{
BpId id;
- // Hard code address space 5 for now.
- call().breakpoint_set_code(_instId, id, it->second->pc, 5, 0, true);
+ Addr pc = it->second->pc;
+ auto space_id = getBpSpaceId(pc);
+ call().breakpoint_set_code(_instId, id, pc, space_id, 0, true);
it->second->id = id;
}
diff --git a/src/arch/arm/fastmodel/iris/thread_context.hh b/src/arch/arm/fastmodel/iris/thread_context.hh
index 4175e93..cab9ebc 100644
--- a/src/arch/arm/fastmodel/iris/thread_context.hh
+++ b/src/arch/arm/fastmodel/iris/thread_context.hh
@@ -119,6 +119,8 @@
void uninstallBp(BpInfoIt it);
void delBp(BpInfoIt it);
+ virtual iris::MemorySpaceId getBpSpaceId(Addr pc) const = 0;
+
iris::IrisErrorCode instanceRegistryChanged(
uint64_t esId, const iris::IrisValueMap &fields, uint64_t time,
