src/cpu/simple/SConscript

# -*- mode:python -*-

# Copyright (c) 2006 The Regents of The University of Michigan
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
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# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
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# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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Import('*')

if env['CONF']['TARGET_ISA'] != 'null':
    SimObject('BaseAtomicSimpleCPU.py', sim_objects=['BaseAtomicSimpleCPU'])
    Source('atomic.cc')

    # The NonCachingSimpleCPU is really an atomic CPU in
    # disguise. It's therefore always enabled when the atomic CPU is
    # enabled.
    SimObject('BaseNonCachingSimpleCPU.py',
            sim_objects=['BaseNonCachingSimpleCPU'])
    Source('noncaching.cc')

    SimObject('BaseTimingSimpleCPU.py', sim_objects=['BaseTimingSimpleCPU'])
    Source('timing.cc')

    DebugFlag('SimpleCPU')

    Source('base.cc')
    SimObject('BaseSimpleCPU.py', sim_objects=['BaseSimpleCPU'])