arch-riscv: Fix disassembling of immediate for U-type instructions
For U-type instructions auipc and lui, the 20-bit immediate is left-shifted
by 12 bits in decoding. While the original Gem5 gives the left-shifted
value directly in disassembly.
This patch fixes the problem by
- Assign the original 20-bit immediate to internal variable "imm".
- Output "imm" directly in disassembly, as how the original Gem5 does.
- Do the left-shift to "imm" later in the function defining of each
instruction, rather than in decoding.
Change-Id: I300e26fd9c79478783c39fcd6ff70ea06db88884
Signed-off-by: Ian Jiang <ianjiang.ict@gmail.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22564
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Alec Roelke <alec.roelke@gmail.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
diff --git a/src/arch/riscv/isa/decoder.isa b/src/arch/riscv/isa/decoder.isa
index 8fcfba6..78cb78c 100644
--- a/src/arch/riscv/isa/decoder.isa
+++ b/src/arch/riscv/isa/decoder.isa
@@ -443,7 +443,7 @@
}
0x05: UOp::auipc({{
- Rd = PC + imm;
+ Rd = PC + (sext<20>(imm) << 12);
}});
0x06: decode FUNCT3 {
@@ -787,7 +787,7 @@
}
0x0d: UOp::lui({{
- Rd = (uint64_t)imm;
+ Rd = (uint64_t)(sext<20>(imm) << 12);
}});
0x0e: decode FUNCT3 {
diff --git a/src/arch/riscv/isa/formats/standard.isa b/src/arch/riscv/isa/formats/standard.isa
index 15d2681..3c71fc8 100644
--- a/src/arch/riscv/isa/formats/standard.isa
+++ b/src/arch/riscv/isa/formats/standard.isa
@@ -341,7 +341,7 @@
def format UOp(code, *opt_flags) {{
regs = ['_destRegIdx[0]']
iop = InstObjParams(name, Name, 'ImmOp<int64_t>',
- {'code': code, 'imm_code': 'imm = sext<20>(IMM20) << 12;',
+ {'code': code, 'imm_code': 'imm = IMM20;',
'regs': ','.join(regs)}, opt_flags)
header_output = ImmDeclare.subst(iop)
decoder_output = ImmConstructor.subst(iop)
