arm: Set the number of FloatRegs to zero.
ARM no longer uses the floating point register file and uses the
vector registers instead. This avoids checkpointing a bunch of unused
registers, making it hard to tell where floating point instructions
are keeping their values, etc.
Change-Id: I23145ba750f1dd9ff5b815395e073c410120840d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22524
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
diff --git a/src/arch/arm/registers.hh b/src/arch/arm/registers.hh
index 75945ad..a97a4ce 100644
--- a/src/arch/arm/registers.hh
+++ b/src/arch/arm/registers.hh
@@ -83,14 +83,13 @@
// The number of single precision floating point registers
const int NumFloatV7ArchRegs = 64;
const int NumFloatV8ArchRegs = 128;
-const int NumFloatSpecialRegs = 32;
const int NumVecV7ArchRegs = 64;
const int NumVecV8ArchRegs = 32;
const int NumVecSpecialRegs = 8;
const int NumVecIntrlvRegs = 4;
const int NumIntRegs = NUM_INTREGS;
-const int NumFloatRegs = NumFloatV8ArchRegs + NumFloatSpecialRegs;
+const int NumFloatRegs = 0; // Float values are stored in the VecRegs
const int NumVecRegs = NumVecV8ArchRegs + NumVecSpecialRegs + NumVecIntrlvRegs;
const int VECREG_UREG0 = 32;
const int NumVecPredRegs = 18; // P0-P15, FFR, UREG0
