commit 2a818db77ab5fe5cc7d716dd2aa88241550045a7
author Giacomo Travaglini <giacomo.travaglini@arm.com> Tue Aug 20 20:48:29 2019 +0100
committer Giacomo Travaglini <giacomo.travaglini@arm.com> Fri Sep 06 20:00:34 2019 +0000
tree 73e57fcf8296bb7244d4fbc5920888725072325c
parent 34f1b771ed911ac8dc9f02ded63add7de3c263ed

arch-arm, dev-arm: MISCREG_ICC_IGRPEN1_EL1 using AA64 banking

Change-Id: Ic08ac1e7f3ebef408a83aa068ce15e9dfe2aa3cd
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20628
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

src/arch/arm/miscregs.cc

diff --git a/src/arch/arm/miscregs.cc b/src/arch/arm/miscregs.cc
index 81bc3ef..bffb444 100644
--- a/src/arch/arm/miscregs.cc
+++ b/src/arch/arm/miscregs.cc
@@ -4646,7 +4646,7 @@
         .allPrivileges().exceptUserMode()
         .mapsTo(MISCREG_ICC_IGRPEN0);
     InitReg(MISCREG_ICC_IGRPEN1_EL1)
-        .banked()
+        .banked64()
         .mapsTo(MISCREG_ICC_IGRPEN1);
     InitReg(MISCREG_ICC_IGRPEN1_EL1_NS)
         .bankedChild()

src/dev/arm/gic_v3_cpu_interface.cc

diff --git a/src/dev/arm/gic_v3_cpu_interface.cc b/src/dev/arm/gic_v3_cpu_interface.cc
index 0d444f1..b793f7c 100644
--- a/src/dev/arm/gic_v3_cpu_interface.cc
+++ b/src/dev/arm/gic_v3_cpu_interface.cc
@@ -191,6 +191,7 @@
               return readMiscReg(MISCREG_ICV_IGRPEN1_EL1);
           }
 
+          value = readBankedMiscReg(MISCREG_ICC_IGRPEN1_EL1);
           break;
       }
 
@@ -1358,7 +1359,8 @@
                                       icc_igrpen1_el3);
           }
 
-          break;
+          setBankedMiscReg(MISCREG_ICC_IGRPEN1_EL1, val);
+          return;
       }
 
       // Virtual Interrupt Group 1 Enable register