commit 2b7d4bd73db443b4ca302213689a673266e856e0
author Gabe Black <gabeblack@google.com> Wed Oct 09 21:04:22 2019 -0700
committer Gabe Black <gabeblack@google.com> Fri Oct 25 22:42:31 2019 +0000
tree 9c111c4416935249eb62b2734336307e94a11a46
parent 1ded8d6d9f829774c16c50c56f1538d4b7711f09

cpu,sim: Get rid of a bunch of conditional compilation for PCEvents.

These can now be built without referring to anything in ThreadContext
and so can be built even with the NULL ISA. This means the pcEventQueue
can be unconditionally built into the System class. Even though the
pcEventQueue is going away, this still makes it possible for System to
be a PCEventScope unconditionally.

Change-Id: Ia342bb7972b1b5ce95033176d72af4bfa343560f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22104
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

src/cpu/SConscript

diff --git a/src/cpu/SConscript b/src/cpu/SConscript
index a8585a7..bd66390 100644
--- a/src/cpu/SConscript
+++ b/src/cpu/SConscript
@@ -72,6 +72,8 @@
     'ExecEffAddr', 'ExecResult', 'ExecMicro', 'ExecMacro', 'ExecFaulting',
     'ExecUser', 'ExecKernel' ])
 
+Source('pc_event.cc')
+
 if env['TARGET_ISA'] == 'null':
     SimObject('IntrControl.py')
     Source('intr_control_noisa.cc')
@@ -99,7 +101,6 @@
 Source('inteltrace.cc')
 Source('intr_control.cc')
 Source('nativetrace.cc')
-Source('pc_event.cc')
 Source('profile.cc')
 Source('quiesce_event.cc')
 Source('reg_class.cc')

src/cpu/pc_event.cc

diff --git a/src/cpu/pc_event.cc b/src/cpu/pc_event.cc
index b4017de..0bb8a41 100644
--- a/src/cpu/pc_event.cc
+++ b/src/cpu/pc_event.cc
@@ -37,8 +37,6 @@
 
 #include "base/debug.hh"
 #include "base/trace.hh"
-#include "cpu/base.hh"
-#include "cpu/thread_context.hh"
 #include "debug/PCEvent.hh"
 #include "sim/core.hh"
 #include "sim/system.hh"

src/sim/system.cc

diff --git a/src/sim/system.cc b/src/sim/system.cc
index 7b8ca87..e993a73 100644
--- a/src/sim/system.cc
+++ b/src/sim/system.cc
@@ -292,7 +292,6 @@
     return id;
 }
 
-#if THE_ISA != NULL_ISA
 bool
 System::schedule(PCEvent *event)
 {
@@ -304,7 +303,6 @@
 {
     return pcEventQueue.remove(event);
 }
-#endif
 
 int
 System::numRunningContexts()

src/sim/system.hh

diff --git a/src/sim/system.hh b/src/sim/system.hh
index c2b8411..8c06603 100644
--- a/src/sim/system.hh
+++ b/src/sim/system.hh
@@ -57,6 +57,7 @@
 #include "base/loader/symtab.hh"
 #include "base/statistics.hh"
 #include "config/the_isa.hh"
+#include "cpu/pc_event.hh"
 #include "enums/MemoryMode.hh"
 #include "mem/mem_master.hh"
 #include "mem/physical.hh"
@@ -68,25 +69,12 @@
 #include "sim/se_signal.hh"
 #include "sim/sim_object.hh"
 
-/**
- * To avoid linking errors with LTO, only include the header if we
- * actually have the definition.
- */
-#if THE_ISA != NULL_ISA
-#include "cpu/pc_event.hh"
-#else
-class PCEvent;
-#endif
-
 class BaseRemoteGDB;
 class KvmVM;
 class ObjectFile;
 class ThreadContext;
 
-class System : public SimObject
-#if THE_ISA != NULL_ISA
-               , public PCEventScope
-#endif
+class System : public SimObject, public PCEventScope
 {
   private:
 
@@ -198,19 +186,15 @@
      */
     unsigned int cacheLineSize() const { return _cacheLineSize; }
 
-#if THE_ISA != NULL_ISA
     PCEventQueue pcEventQueue;
-#endif
 
     std::vector<ThreadContext *> threadContexts;
     const bool multiThread;
 
     using SimObject::schedule;
 
-#if THE_ISA != NULL_ISA
     bool schedule(PCEvent *event) override;
     bool remove(PCEvent *event) override;
-#endif
 
     ThreadContext *getThreadContext(ContextID tid) const
     {
@@ -502,13 +486,11 @@
     {
         Addr addr M5_VAR_USED = 0; // initialize only to avoid compiler warning
 
-#if THE_ISA != NULL_ISA
         if (symtab->findAddress(lbl, addr)) {
             T *ev = new T(this, desc, fixFuncEventAddr(addr),
                           std::forward<Args>(args)...);
             return ev;
         }
-#endif
 
         return NULL;
     }