| commit | 2dd1842a67fe75c8705c1b9136f9d91defdc24cb | [log] [tgz] |
|---|---|---|
| author | Giacomo Travaglini <giacomo.travaglini@arm.com> | Thu Nov 07 09:45:01 2019 +0000 |
| committer | Giacomo Travaglini <giacomo.travaglini@arm.com> | Mon Nov 18 09:45:55 2019 +0000 |
| tree | 1cf50e62554fde2d17edd0b1106061a1e5a11df5 | |
| parent | dd77848e2cddfaacf8105fd8d3110d708d41b125 [diff] |
arch-arm: Fix short descriptors cacheability during table walks This implies checking for the SCTLR.C bit TTBR1.IRGN0 bits. Change-Id: I341faf85692ce2d2b4afd30a2f4aabac0e133192 Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22724 Tested-by: kokoro <noreply+kokoro@google.com>