arch-arm: Fix short descriptors cacheability during table walks
This implies checking for the SCTLR.C bit TTBR1.IRGN0 bits.
Change-Id: I341faf85692ce2d2b4afd30a2f4aabac0e133192
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/22724
Tested-by: kokoro <noreply+kokoro@google.com>
diff --git a/src/arch/arm/table_walker.cc b/src/arch/arm/table_walker.cc
index ff4e675..52e6be7 100644
--- a/src/arch/arm/table_walker.cc
+++ b/src/arch/arm/table_walker.cc
@@ -456,6 +456,15 @@
{
Addr ttbr = 0;
+ // For short descriptors, translation configs are held in
+ // TTBR1.
+ RegVal ttbr1 = currState->tc->readMiscReg(snsBankedIndex(
+ MISCREG_TTBR1, currState->tc, !currState->isSecure));
+
+ const auto irgn0_mask = 0x1;
+ const auto irgn1_mask = 0x40;
+ currState->isUncacheable = (ttbr1 & (irgn0_mask | irgn1_mask)) == 0;
+
// If translation isn't enabled, we shouldn't be here
assert(currState->sctlr.m || isStage2);
const bool is_atomic = currState->req->isAtomic();
@@ -505,8 +514,7 @@
ArmFault::TranslationLL + L1, isStage2,
ArmFault::VmsaTran);
}
- ttbr = currState->tc->readMiscReg(snsBankedIndex(
- MISCREG_TTBR1, currState->tc, !currState->isSecure));
+ ttbr = ttbr1;
currState->ttbcr.n = 0;
}
@@ -533,7 +541,7 @@
}
Request::Flags flag = Request::PT_WALK;
- if (currState->sctlr.c == 0) {
+ if (currState->sctlr.c == 0 || currState->isUncacheable) {
flag.set(Request::UNCACHEABLE);
}
@@ -1545,6 +1553,11 @@
}
Request::Flags flag = Request::PT_WALK;
+
+ if (currState->sctlr.c == 0 || currState->isUncacheable) {
+ flag.set(Request::UNCACHEABLE);
+ }
+
if (currState->isSecure)
flag.set(Request::SECURE);