src/arch/arm/isa/formats/crypto64.isa

// -*- mode:c++ -*-

// Copyright (c) 2018 ARM Limited
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//
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let {{
    header_output = '''
    StaticInstPtr
    decodeCryptoAES(ExtMachInst machInst);

    StaticInstPtr
    decodeCryptoThreeRegSHA(ExtMachInst machInst);

    StaticInstPtr
    decodeCryptoTwoRegSHA(ExtMachInst machInst);
    '''

    decoder_output = '''

    StaticInstPtr
    decodeCryptoAES(ExtMachInst machInst)
    {
        const auto opcode = bits(machInst, 16, 12);
        const auto size = bits(machInst, 23, 22);

        RegIndex rd = (RegIndex) (uint8_t) bits(machInst, 4, 0);
        RegIndex rn = (RegIndex) (uint8_t) bits(machInst, 9, 5);

        if (size) {
            // UNALLOCATED
            return new Unknown64(machInst);
        } else {
            switch (opcode) {
              case 0x4: return new AESE64(machInst, rd, rd, rn);
              case 0x5: return new AESD64(machInst, rd, rd, rn);
              case 0x6: return new AESMC64(machInst, rd, rn);
              case 0x7: return new AESIMC64(machInst, rd, rn);
              default: return new Unknown64(machInst);
            }
        }
    }

    StaticInstPtr
    decodeCryptoTwoRegSHA(ExtMachInst machInst)
    {
        const auto opcode = bits(machInst, 16, 12);
        const auto size = bits(machInst, 23, 22);

        RegIndex rd = (RegIndex) (uint8_t) bits(machInst, 4, 0);
        RegIndex rn = (RegIndex) (uint8_t) bits(machInst, 9, 5);

        if (size) {
            // UNALLOCATED
            return new Unknown64(machInst);
        } else {
            switch (opcode) {
              case 0x0: return new SHA1H64(machInst, rd, rn);
              case 0x1: return new SHA1SU164(machInst, rd, rn);
              case 0x2: return new SHA256SU064(machInst, rd, rn);
              default: return new Unknown64(machInst);
            }
        }
    }

    StaticInstPtr
    decodeCryptoThreeRegSHA(ExtMachInst machInst)
    {
        const auto opcode = bits(machInst, 14, 12);
        const auto size = bits(machInst, 23, 22);

        RegIndex rd = (RegIndex) (uint8_t) bits(machInst, 4, 0);
        RegIndex rn = (RegIndex) (uint8_t) bits(machInst, 9, 5);
        RegIndex rm = (RegIndex) (uint8_t) bits(machInst, 20, 16);

        if (size) {
            // UNALLOCATED
            return new Unknown64(machInst);
        } else {
            switch (opcode) {
              case 0x0: return new SHA1C64(machInst, rd, rn, rm);
              case 0x1: return new SHA1P64(machInst, rd, rn, rm);
              case 0x2: return new SHA1M64(machInst, rd, rn, rm);
              case 0x3: return new SHA1SU064(machInst, rd, rn, rm);
              case 0x4: return new SHA256H64(machInst, rd, rn, rm);
              case 0x5: return new SHA256H264(machInst, rd, rn, rm);
              case 0x6: return new SHA256SU164(machInst, rd, rn, rm);
              default: return new Unknown64(machInst);
            }
        }
    }
   '''
}};