misc: Replace namespace Trace with lowercase trace
This is what the coding style demands
Change-Id: Ida6a71ad9c2c02cccd584bbaf37a6da751c5b856
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/63891
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Daniel Carvalho <odanrc@yahoo.com.br>
diff --git a/src/arch/arm/ArmNativeTrace.py b/src/arch/arm/ArmNativeTrace.py
index 469b539..0c795a6 100644
--- a/src/arch/arm/ArmNativeTrace.py
+++ b/src/arch/arm/ArmNativeTrace.py
@@ -31,7 +31,7 @@
class ArmNativeTrace(NativeTrace):
type = "ArmNativeTrace"
- cxx_class = "gem5::Trace::ArmNativeTrace"
+ cxx_class = "gem5::trace::ArmNativeTrace"
cxx_header = "arch/arm/nativetrace.hh"
stop_on_pc_error = Param.Bool(
True, "Stop M5 if it and statetrace's pcs are different"
diff --git a/src/arch/arm/insts/misc.cc b/src/arch/arm/insts/misc.cc
index ee40019..97a1b8b 100644
--- a/src/arch/arm/insts/misc.cc
+++ b/src/arch/arm/insts/misc.cc
@@ -361,7 +361,7 @@
}
Fault
-McrMrcMiscInst::execute(ExecContext *xc, Trace::InstRecord *traceData) const
+McrMrcMiscInst::execute(ExecContext *xc, trace::InstRecord *traceData) const
{
return mcrMrc15Trap(miscReg, machInst, xc->tcBase(), iss);
}
@@ -380,7 +380,7 @@
{}
Fault
-McrMrcImplDefined::execute(ExecContext *xc, Trace::InstRecord *traceData) const
+McrMrcImplDefined::execute(ExecContext *xc, trace::InstRecord *traceData) const
{
Fault fault = mcrMrc15Trap(miscReg, machInst, xc->tcBase(), iss);
if (fault != NoFault) {
diff --git a/src/arch/arm/insts/misc.hh b/src/arch/arm/insts/misc.hh
index d9f24b9..6c6e4e1 100644
--- a/src/arch/arm/insts/misc.hh
+++ b/src/arch/arm/insts/misc.hh
@@ -414,7 +414,7 @@
uint64_t _iss, ArmISA::MiscRegIndex _miscReg);
Fault execute(ExecContext *xc,
- Trace::InstRecord *traceData) const override;
+ trace::InstRecord *traceData) const override;
std::string generateDisassembly(
Addr pc, const loader::SymbolTable *symtab) const override;
@@ -432,7 +432,7 @@
uint64_t _iss, ArmISA::MiscRegIndex _miscReg);
Fault execute(ExecContext *xc,
- Trace::InstRecord *traceData) const override;
+ trace::InstRecord *traceData) const override;
std::string generateDisassembly(
Addr pc, const loader::SymbolTable *symtab) const override;
diff --git a/src/arch/arm/insts/misc64.cc b/src/arch/arm/insts/misc64.cc
index 273e229..58d6bd3 100644
--- a/src/arch/arm/insts/misc64.cc
+++ b/src/arch/arm/insts/misc64.cc
@@ -190,7 +190,7 @@
Fault
MiscRegImplDefined64::execute(ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
auto tc = xc->tcBase();
const CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
diff --git a/src/arch/arm/insts/misc64.hh b/src/arch/arm/insts/misc64.hh
index eefc16f..b7b66c2 100644
--- a/src/arch/arm/insts/misc64.hh
+++ b/src/arch/arm/insts/misc64.hh
@@ -226,7 +226,7 @@
protected:
Fault execute(ExecContext *xc,
- Trace::InstRecord *traceData) const override;
+ trace::InstRecord *traceData) const override;
std::string generateDisassembly(
Addr pc, const loader::SymbolTable *symtab) const override;
diff --git a/src/arch/arm/insts/pred_inst.hh b/src/arch/arm/insts/pred_inst.hh
index 29581a9..da3db6c 100644
--- a/src/arch/arm/insts/pred_inst.hh
+++ b/src/arch/arm/insts/pred_inst.hh
@@ -371,7 +371,7 @@
}
Fault
- execute(ExecContext *, Trace::InstRecord *) const override
+ execute(ExecContext *, trace::InstRecord *) const override
{
panic("Execute method called when it shouldn't!");
}
diff --git a/src/arch/arm/insts/pseudo.cc b/src/arch/arm/insts/pseudo.cc
index ca5e594..3d017c1 100644
--- a/src/arch/arm/insts/pseudo.cc
+++ b/src/arch/arm/insts/pseudo.cc
@@ -58,7 +58,7 @@
}
Fault
-DecoderFaultInst::execute(ExecContext *xc, Trace::InstRecord *traceData) const
+DecoderFaultInst::execute(ExecContext *xc, trace::InstRecord *traceData) const
{
const Addr pc = xc->pcState().instAddr();
@@ -130,7 +130,7 @@
}
Fault
-FailUnimplemented::execute(ExecContext *xc, Trace::InstRecord *traceData) const
+FailUnimplemented::execute(ExecContext *xc, trace::InstRecord *traceData) const
{
return std::make_shared<UndefinedInstruction>(machInst, false, mnemonic);
}
@@ -166,7 +166,7 @@
}
Fault
-WarnUnimplemented::execute(ExecContext *xc, Trace::InstRecord *traceData) const
+WarnUnimplemented::execute(ExecContext *xc, trace::InstRecord *traceData) const
{
if (!warned) {
warn("\tinstruction '%s' unimplemented\n",
@@ -190,7 +190,7 @@
{}
Fault
-IllegalExecInst::execute(ExecContext *xc, Trace::InstRecord *traceData) const
+IllegalExecInst::execute(ExecContext *xc, trace::InstRecord *traceData) const
{
return std::make_shared<IllegalInstSetStateFault>();
}
@@ -200,7 +200,7 @@
{ }
Fault
-DebugStep::execute(ExecContext *xc, Trace::InstRecord *traceData) const
+DebugStep::execute(ExecContext *xc, trace::InstRecord *traceData) const
{
PCState pc_state = xc->pcState().as<PCState>();
pc_state.debugStep(false);
diff --git a/src/arch/arm/insts/pseudo.hh b/src/arch/arm/insts/pseudo.hh
index 215f965..981fa38 100644
--- a/src/arch/arm/insts/pseudo.hh
+++ b/src/arch/arm/insts/pseudo.hh
@@ -57,7 +57,7 @@
DecoderFaultInst(ArmISA::ExtMachInst _machInst);
Fault execute(ExecContext *xc,
- Trace::InstRecord *traceData) const override;
+ trace::InstRecord *traceData) const override;
std::string generateDisassembly(
Addr pc, const loader::SymbolTable *symtab) const override;
@@ -83,7 +83,7 @@
const std::string& _fullMnemonic);
Fault execute(ExecContext *xc,
- Trace::InstRecord *traceData) const override;
+ trace::InstRecord *traceData) const override;
std::string generateDisassembly(
Addr pc, const loader::SymbolTable *symtab) const override;
@@ -113,7 +113,7 @@
const std::string& _fullMnemonic);
Fault execute(ExecContext *xc,
- Trace::InstRecord *traceData) const override;
+ trace::InstRecord *traceData) const override;
std::string generateDisassembly(
Addr pc, const loader::SymbolTable *symtab) const override;
@@ -132,7 +132,7 @@
IllegalExecInst(ArmISA::ExtMachInst _machInst);
Fault execute(ExecContext *xc,
- Trace::InstRecord *traceData) const override;
+ trace::InstRecord *traceData) const override;
};
class DebugStep : public ArmISA::ArmStaticInst
@@ -141,7 +141,7 @@
DebugStep(ArmISA::ExtMachInst _machInst);
Fault execute(ExecContext *xc,
- Trace::InstRecord *traceData) const override;
+ trace::InstRecord *traceData) const override;
};
} // namespace gem5
diff --git a/src/arch/arm/insts/sve_macromem.hh b/src/arch/arm/insts/sve_macromem.hh
index 8e94fa4..e7d5608 100644
--- a/src/arch/arm/insts/sve_macromem.hh
+++ b/src/arch/arm/insts/sve_macromem.hh
@@ -89,7 +89,7 @@
}
Fault
- execute(ExecContext *, Trace::InstRecord *) const override
+ execute(ExecContext *, trace::InstRecord *) const override
{
panic("Execute method called when it shouldn't!");
return NoFault;
@@ -162,7 +162,7 @@
}
Fault
- execute(ExecContext *, Trace::InstRecord *) const override
+ execute(ExecContext *, trace::InstRecord *) const override
{
panic("Execute method called when it shouldn't!");
return NoFault;
@@ -235,7 +235,7 @@
}
Fault
- execute(ExecContext *, Trace::InstRecord *) const override
+ execute(ExecContext *, trace::InstRecord *) const override
{
panic("Execute method called when it shouldn't!");
return NoFault;
@@ -309,7 +309,7 @@
}
Fault
- execute(ExecContext *, Trace::InstRecord *) const override
+ execute(ExecContext *, trace::InstRecord *) const override
{
panic("Execute method called when it shouldn't!");
return NoFault;
@@ -409,7 +409,7 @@
}
Fault
- execute(ExecContext *, Trace::InstRecord *) const override
+ execute(ExecContext *, trace::InstRecord *) const override
{
panic("Execute method called when it shouldn't!");
return NoFault;
@@ -514,7 +514,7 @@
}
Fault
- execute(ExecContext *, Trace::InstRecord *) const override
+ execute(ExecContext *, trace::InstRecord *) const override
{
panic("Execute method called when it shouldn't!");
return NoFault;
diff --git a/src/arch/arm/insts/tme64.cc b/src/arch/arm/insts/tme64.cc
index 5632dfa..adcc8dd 100644
--- a/src/arch/arm/insts/tme64.cc
+++ b/src/arch/arm/insts/tme64.cc
@@ -89,14 +89,14 @@
Fault
MicroTfence64::execute(
- ExecContext *xc, Trace::InstRecord *traceData) const
+ ExecContext *xc, trace::InstRecord *traceData) const
{
return NoFault;
}
Fault
MicroTfence64::initiateAcc(ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
panic("tfence should not have memory semantics");
@@ -105,7 +105,7 @@
Fault
MicroTfence64::completeAcc(PacketPtr pkt, ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
panic("tfence should not have memory semantics");
@@ -134,7 +134,7 @@
Fault
Tstart64::execute(
- ExecContext *xc, Trace::InstRecord *traceData) const
+ ExecContext *xc, trace::InstRecord *traceData) const
{
panic("TME is not supported with atomic memory");
@@ -171,7 +171,7 @@
Fault
Tcancel64::execute(
- ExecContext *xc, Trace::InstRecord *traceData) const
+ ExecContext *xc, trace::InstRecord *traceData) const
{
panic("TME is not supported with atomic memory");
@@ -201,7 +201,7 @@
}
Fault
-MicroTcommit64::execute(ExecContext *xc, Trace::InstRecord *traceData) const
+MicroTcommit64::execute(ExecContext *xc, trace::InstRecord *traceData) const
{
panic("TME is not supported with atomic memory");
diff --git a/src/arch/arm/insts/tme64.hh b/src/arch/arm/insts/tme64.hh
index c8994f3..8588eaf 100644
--- a/src/arch/arm/insts/tme64.hh
+++ b/src/arch/arm/insts/tme64.hh
@@ -106,9 +106,9 @@
public:
Tstart64(ArmISA::ExtMachInst, RegIndex);
- Fault execute(ExecContext *, Trace::InstRecord *) const;
- Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
- Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
+ Fault execute(ExecContext *, trace::InstRecord *) const;
+ Fault initiateAcc(ExecContext *, trace::InstRecord *) const;
+ Fault completeAcc(PacketPtr, ExecContext *, trace::InstRecord *) const;
};
class Ttest64 : public TmeRegNone64
@@ -119,7 +119,7 @@
public:
Ttest64(ArmISA::ExtMachInst, RegIndex);
- Fault execute(ExecContext *, Trace::InstRecord *) const;
+ Fault execute(ExecContext *, trace::InstRecord *) const;
};
class Tcancel64 : public TmeImmOp64
@@ -127,9 +127,9 @@
public:
Tcancel64(ArmISA::ExtMachInst, uint64_t);
- Fault execute(ExecContext *, Trace::InstRecord *) const;
- Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
- Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
+ Fault execute(ExecContext *, trace::InstRecord *) const;
+ Fault initiateAcc(ExecContext *, trace::InstRecord *) const;
+ Fault completeAcc(PacketPtr, ExecContext *, trace::InstRecord *) const;
};
class MicroTfence64 : public MicroTmeBasic64
@@ -137,9 +137,9 @@
public:
MicroTfence64(ArmISA::ExtMachInst);
- Fault execute(ExecContext *, Trace::InstRecord *) const;
- Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
- Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
+ Fault execute(ExecContext *, trace::InstRecord *) const;
+ Fault initiateAcc(ExecContext *, trace::InstRecord *) const;
+ Fault completeAcc(PacketPtr, ExecContext *, trace::InstRecord *) const;
};
class MicroTcommit64 : public MicroTmeBasic64
@@ -147,9 +147,9 @@
public:
MicroTcommit64(ArmISA::ExtMachInst);
- Fault execute(ExecContext *, Trace::InstRecord *) const;
- Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
- Fault completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const;
+ Fault execute(ExecContext *, trace::InstRecord *) const;
+ Fault initiateAcc(ExecContext *, trace::InstRecord *) const;
+ Fault completeAcc(PacketPtr, ExecContext *, trace::InstRecord *) const;
};
diff --git a/src/arch/arm/insts/tme64classic.cc b/src/arch/arm/insts/tme64classic.cc
index c6c1e54..0c944f4 100644
--- a/src/arch/arm/insts/tme64classic.cc
+++ b/src/arch/arm/insts/tme64classic.cc
@@ -47,7 +47,7 @@
Fault
Tstart64::initiateAcc(ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
return std::make_shared<UndefinedInstruction>(machInst,
false,
@@ -56,7 +56,7 @@
Fault
Tstart64::completeAcc(PacketPtr pkt, ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
return std::make_shared<UndefinedInstruction>(machInst,
false,
@@ -65,7 +65,7 @@
Fault
Ttest64::execute(
- ExecContext *xc, Trace::InstRecord *traceData) const
+ ExecContext *xc, trace::InstRecord *traceData) const
{
return std::make_shared<UndefinedInstruction>(machInst,
false,
@@ -74,7 +74,7 @@
Fault
Tcancel64::initiateAcc(ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
return std::make_shared<UndefinedInstruction>(machInst,
false,
@@ -83,7 +83,7 @@
Fault
Tcancel64::completeAcc(PacketPtr pkt, ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
return std::make_shared<UndefinedInstruction>(machInst,
false,
@@ -92,7 +92,7 @@
Fault
MicroTcommit64::initiateAcc(ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
return std::make_shared<UndefinedInstruction>(machInst,
false,
@@ -101,7 +101,7 @@
Fault
MicroTcommit64::completeAcc(PacketPtr pkt, ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
return std::make_shared<UndefinedInstruction>(machInst,
false,
diff --git a/src/arch/arm/insts/tme64ruby.cc b/src/arch/arm/insts/tme64ruby.cc
index 9bde2d9..1bd5d9a 100644
--- a/src/arch/arm/insts/tme64ruby.cc
+++ b/src/arch/arm/insts/tme64ruby.cc
@@ -52,7 +52,7 @@
Fault
Tstart64::initiateAcc(ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
Fault fault = NoFault;
const uint64_t htm_depth = xc->getHtmTransactionalDepth();
@@ -85,7 +85,7 @@
Fault
Tstart64::completeAcc(PacketPtr pkt, ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
Fault fault = NoFault;
uint64_t Mem;
@@ -133,7 +133,7 @@
}
Fault
-Ttest64::execute(ExecContext *xc, Trace::InstRecord *traceData) const
+Ttest64::execute(ExecContext *xc, trace::InstRecord *traceData) const
{
Fault fault = NoFault;
uint64_t Dest64 = 0;
@@ -163,7 +163,7 @@
}
Fault
-Tcancel64::initiateAcc(ExecContext *xc, Trace::InstRecord *traceData) const
+Tcancel64::initiateAcc(ExecContext *xc, trace::InstRecord *traceData) const
{
Fault fault = NoFault;
@@ -182,7 +182,7 @@
Fault
Tcancel64::completeAcc(PacketPtr pkt, ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
Fault fault = NoFault;
uint64_t Mem;
@@ -209,7 +209,7 @@
Fault
MicroTcommit64::initiateAcc(ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
Fault fault = NoFault;
const uint64_t htm_depth = xc->getHtmTransactionalDepth();
@@ -238,7 +238,7 @@
Fault
MicroTcommit64::completeAcc(PacketPtr pkt, ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
Fault fault = NoFault;
uint64_t Mem;
diff --git a/src/arch/arm/isa/templates/basic.isa b/src/arch/arm/isa/templates/basic.isa
index d0bc82d..3620c00 100644
--- a/src/arch/arm/isa/templates/basic.isa
+++ b/src/arch/arm/isa/templates/basic.isa
@@ -51,7 +51,7 @@
public:
/// Constructor.
%(class_name)s(ExtMachInst machInst);
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -84,7 +84,7 @@
def template BasicExecute {{
Fault
%(class_name)s::execute(
- ExecContext *xc, Trace::InstRecord *traceData) const
+ ExecContext *xc, trace::InstRecord *traceData) const
{
Fault fault = NoFault;
diff --git a/src/arch/arm/isa/templates/branch.isa b/src/arch/arm/isa/templates/branch.isa
index 2ba16f1..7d0efba 100644
--- a/src/arch/arm/isa/templates/branch.isa
+++ b/src/arch/arm/isa/templates/branch.isa
@@ -45,7 +45,7 @@
// Constructor
%(class_name)s(ExtMachInst machInst, int32_t _imm,
ConditionCode _condCode);
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
std::unique_ptr<PCStateBase> branchTarget(
const PCStateBase &branch_pc) const override;
@@ -82,7 +82,7 @@
// Constructor
%(class_name)s(ExtMachInst machInst, RegIndex _op1,
ConditionCode _condCode);
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -115,10 +115,10 @@
public:
// Constructor
%(class_name)s(ExtMachInst machInst, RegIndex _op1, RegIndex _op2);
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
- Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
+ Fault initiateAcc(ExecContext *, trace::InstRecord *) const override;
Fault completeAcc(PacketPtr, ExecContext *,
- Trace::InstRecord *) const override;
+ trace::InstRecord *) const override;
};
}};
@@ -149,7 +149,7 @@
public:
// Constructor
%(class_name)s(ExtMachInst machInst, int32_t imm, RegIndex _op1);
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
std::unique_ptr<PCStateBase> branchTarget(
const PCStateBase &branch_pc) const override;
diff --git a/src/arch/arm/isa/templates/branch64.isa b/src/arch/arm/isa/templates/branch64.isa
index b3914e0..99edc8e 100644
--- a/src/arch/arm/isa/templates/branch64.isa
+++ b/src/arch/arm/isa/templates/branch64.isa
@@ -44,7 +44,7 @@
public:
// Constructor
%(class_name)s(ExtMachInst machInst, int64_t _imm);
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -67,7 +67,7 @@
// Constructor
%(class_name)s(ExtMachInst machInst, int64_t _imm,
ConditionCode _condCode);
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -90,7 +90,7 @@
public:
// Constructor
%(class_name)s(ExtMachInst machInst, RegIndex _op1);
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -112,7 +112,7 @@
public:
// Constructor
%(class_name)s(ExtMachInst machInst, RegIndex _op1, RegIndex _op2);
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -135,7 +135,7 @@
public:
// Constructor
%(class_name)s(ExtMachInst machInst, int64_t imm, RegIndex _op1);
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -159,7 +159,7 @@
// Constructor
%(class_name)s(ExtMachInst machInst, int64_t _imm1, int64_t _imm2,
RegIndex _op1);
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
diff --git a/src/arch/arm/isa/templates/crypto.isa b/src/arch/arm/isa/templates/crypto.isa
index 417d643..f2080a2 100644
--- a/src/arch/arm/isa/templates/crypto.isa
+++ b/src/arch/arm/isa/templates/crypto.isa
@@ -39,7 +39,7 @@
// storage/extraction here is fixed as constants.
def template CryptoPredOpExecute {{
Fault %(class_name)s::execute(ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
Fault fault = NoFault;
%(op_decl)s;
diff --git a/src/arch/arm/isa/templates/data64.isa b/src/arch/arm/isa/templates/data64.isa
index 69c4b64..99bda0b 100644
--- a/src/arch/arm/isa/templates/data64.isa
+++ b/src/arch/arm/isa/templates/data64.isa
@@ -45,7 +45,7 @@
// Constructor
%(class_name)s(ExtMachInst machInst, RegIndex _dest,
RegIndex _op1, uint64_t _imm);
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -72,7 +72,7 @@
%(class_name)s(ExtMachInst machInst, RegIndex _dest,
RegIndex _op1, RegIndex _op2,
int32_t _shiftAmt, ArmShiftType _shiftType);
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -100,7 +100,7 @@
%(class_name)s(ExtMachInst machInst, RegIndex _dest,
RegIndex _op1, RegIndex _op2,
ArmExtendType _extendType, int32_t _shiftAmt);
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -126,7 +126,7 @@
public:
// Constructor
%(class_name)s(ExtMachInst machInst, RegIndex _dest, RegIndex _op1);
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -150,7 +150,7 @@
// Constructor
%(class_name)s(ExtMachInst machInst, RegIndex _dest,
RegIndex _op1, RegIndex _op2);
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -175,7 +175,7 @@
// Constructor
%(class_name)s(ExtMachInst machInst, RegIndex _dest,
RegIndex _op1, RegIndex _op2, uint64_t _imm);
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -201,7 +201,7 @@
// Constructor
%(class_name)s(ExtMachInst machInst, RegIndex _dest,
RegIndex _op1, RegIndex _op2, RegIndex _op3);
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -227,7 +227,7 @@
// Constructor
%(class_name)s(ExtMachInst machInst, RegIndex _op1,
uint64_t _imm, ConditionCode _condCode, uint8_t _defCc);
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -253,7 +253,7 @@
// Constructor
%(class_name)s(ExtMachInst machInst, RegIndex _op1,
RegIndex _op2, ConditionCode _condCode, uint8_t _defCc);
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -280,7 +280,7 @@
%(class_name)s(ExtMachInst machInst, RegIndex _dest,
RegIndex _op1, RegIndex _op2,
ConditionCode _condCode);
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
diff --git a/src/arch/arm/isa/templates/macromem.isa b/src/arch/arm/isa/templates/macromem.isa
index dfda85c..5138001 100644
--- a/src/arch/arm/isa/templates/macromem.isa
+++ b/src/arch/arm/isa/templates/macromem.isa
@@ -53,10 +53,10 @@
%(class_name)s(ExtMachInst machInst,
RegIndex _ura, RegIndex _urb, bool _up,
uint8_t _imm);
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
- Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
+ Fault initiateAcc(ExecContext *, trace::InstRecord *) const override;
Fault completeAcc(PacketPtr, ExecContext *,
- Trace::InstRecord *) const override;
+ trace::InstRecord *) const override;
};
}};
@@ -90,10 +90,10 @@
%(class_name)s(ExtMachInst machInst,
RegIndex _dreg1, RegIndex _dreg2, RegIndex _base,
bool _up, uint8_t _imm);
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
- Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
+ Fault initiateAcc(ExecContext *, trace::InstRecord *) const override;
Fault completeAcc(PacketPtr, ExecContext *,
- Trace::InstRecord *) const override;
+ trace::InstRecord *) const override;
};
}};
@@ -145,10 +145,10 @@
}
}
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
- Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
+ Fault initiateAcc(ExecContext *, trace::InstRecord *) const override;
Fault completeAcc(PacketPtr, ExecContext *,
- Trace::InstRecord *) const override;
+ trace::InstRecord *) const override;
};
}};
@@ -169,7 +169,7 @@
RegIndex _ura,
RegIndex _urb,
RegIndex _urc);
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -202,19 +202,19 @@
def template MicroNeonMemExecDeclare {{
template
Fault %(class_name)s<%(targs)s>::execute(
- ExecContext *, Trace::InstRecord *) const;
+ ExecContext *, trace::InstRecord *) const;
template
Fault %(class_name)s<%(targs)s>::initiateAcc(
- ExecContext *, Trace::InstRecord *) const;
+ ExecContext *, trace::InstRecord *) const;
template
Fault %(class_name)s<%(targs)s>::completeAcc(PacketPtr,
- ExecContext *, Trace::InstRecord *) const;
+ ExecContext *, trace::InstRecord *) const;
}};
def template MicroNeonExecDeclare {{
template
Fault %(class_name)s<%(targs)s>::execute(
- ExecContext *, Trace::InstRecord *) const;
+ ExecContext *, trace::InstRecord *) const;
}};
////////////////////////////////////////////////////////////////////
@@ -244,14 +244,14 @@
}
}
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
def template MicroNeonMixExecute {{
template <class Element>
Fault %(class_name)s<Element>::execute(ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
Fault fault = NoFault;
uint64_t resTemp = 0;
@@ -299,7 +299,7 @@
}
}
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -317,7 +317,7 @@
public:
%(class_name)s(ExtMachInst machInst,
RegIndex _ura, RegIndex _urb);
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
def template MicroIntMovConstructor {{
@@ -352,7 +352,7 @@
%(class_name)s(ExtMachInst machInst,
RegIndex _ura, RegIndex _urb,
int32_t _imm);
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -397,7 +397,7 @@
%(class_name)s(ExtMachInst machInst,
RegIndex _ura, RegIndex _urb, RegIndex _urc,
int32_t _shiftAmt, ArmShiftType _shiftType);
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -423,7 +423,7 @@
%(class_name)s(ExtMachInst machInst,
RegIndex _ura, RegIndex _urb, RegIndex _urc,
ArmExtendType _type, uint32_t _shiftAmt);
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
diff --git a/src/arch/arm/isa/templates/mem.isa b/src/arch/arm/isa/templates/mem.isa
index 41b1586..43969b6 100644
--- a/src/arch/arm/isa/templates/mem.isa
+++ b/src/arch/arm/isa/templates/mem.isa
@@ -42,7 +42,7 @@
def template PanicExecute {{
Fault
%(class_name)s::execute(ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
panic("Execute function executed when it shouldn't be!\n");
return NoFault;
@@ -52,7 +52,7 @@
def template PanicInitiateAcc {{
Fault
%(class_name)s::initiateAcc(ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
panic("InitiateAcc function executed when it shouldn't be!\n");
return NoFault;
@@ -62,7 +62,7 @@
def template PanicCompleteAcc {{
Fault
%(class_name)s::completeAcc(PacketPtr pkt, ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
panic("CompleteAcc function executed when it shouldn't be!\n");
return NoFault;
@@ -73,7 +73,7 @@
def template SwapExecute {{
Fault
%(class_name)s::execute(ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
@@ -109,7 +109,7 @@
def template SwapInitiateAcc {{
Fault
%(class_name)s::initiateAcc(ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
@@ -137,7 +137,7 @@
def template SwapCompleteAcc {{
Fault
%(class_name)s::completeAcc(PacketPtr pkt, ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
Fault fault = NoFault;
@@ -163,7 +163,7 @@
def template LoadExecute {{
Fault
%(class_name)s::execute(ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
@@ -194,7 +194,7 @@
template <class Element>
Fault
%(class_name)s<Element>::execute(
- ExecContext *xc, Trace::InstRecord *traceData) const
+ ExecContext *xc, trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
@@ -230,7 +230,7 @@
def template StoreExecute {{
Fault
%(class_name)s::execute(ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
@@ -264,7 +264,7 @@
template <class Element>
Fault
%(class_name)s<Element>::execute(
- ExecContext *xc, Trace::InstRecord *traceData) const
+ ExecContext *xc, trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
@@ -303,7 +303,7 @@
def template StoreExExecute {{
Fault
%(class_name)s::execute(ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
@@ -342,7 +342,7 @@
def template StoreExInitiateAcc {{
Fault
%(class_name)s::initiateAcc(ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
@@ -371,7 +371,7 @@
def template StoreInitiateAcc {{
Fault
%(class_name)s::initiateAcc(ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
@@ -401,7 +401,7 @@
template <class Element>
Fault
%(class_name)s<Element>::initiateAcc(
- ExecContext *xc, Trace::InstRecord *traceData) const
+ ExecContext *xc, trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
@@ -434,7 +434,7 @@
def template LoadInitiateAcc {{
Fault
%(class_name)s::initiateAcc(ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
@@ -460,7 +460,7 @@
template <class Element>
Fault
%(class_name)s<Element>::initiateAcc(
- ExecContext *xc, Trace::InstRecord *traceData) const
+ ExecContext *xc, trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
@@ -487,7 +487,7 @@
def template LoadCompleteAcc {{
Fault
%(class_name)s::completeAcc(PacketPtr pkt, ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
Fault fault = NoFault;
@@ -515,7 +515,7 @@
template <class Element>
Fault
%(class_name)s<Element>::completeAcc(
- PacketPtr pkt, ExecContext *xc, Trace::InstRecord *traceData) const
+ PacketPtr pkt, ExecContext *xc, trace::InstRecord *traceData) const
{
Fault fault = NoFault;
@@ -543,7 +543,7 @@
def template StoreCompleteAcc {{
Fault
%(class_name)s::completeAcc(PacketPtr pkt, ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
return NoFault;
}
@@ -553,7 +553,7 @@
template <class Element>
Fault
%(class_name)s<Element>::completeAcc(
- PacketPtr pkt, ExecContext *xc, Trace::InstRecord *traceData) const
+ PacketPtr pkt, ExecContext *xc, trace::InstRecord *traceData) const
{
return NoFault;
}
@@ -562,7 +562,7 @@
def template StoreExCompleteAcc {{
Fault
%(class_name)s::completeAcc(PacketPtr pkt, ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
Fault fault = NoFault;
@@ -596,10 +596,10 @@
%(class_name)s(ExtMachInst machInst,
uint32_t _base, int _mode, bool _wb);
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
- Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
+ Fault initiateAcc(ExecContext *, trace::InstRecord *) const override;
Fault completeAcc(PacketPtr, ExecContext *,
- Trace::InstRecord *) const override;
+ trace::InstRecord *) const override;
};
}};
@@ -617,10 +617,10 @@
%(class_name)s(ExtMachInst machInst,
uint32_t _regMode, int _mode, bool _wb);
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
- Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
+ Fault initiateAcc(ExecContext *, trace::InstRecord *) const override;
Fault completeAcc(PacketPtr, ExecContext *,
- Trace::InstRecord *) const override;
+ trace::InstRecord *) const override;
};
}};
@@ -638,10 +638,10 @@
%(class_name)s(ExtMachInst machInst,
uint32_t _dest, uint32_t _op1, uint32_t _base);
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
- Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
+ Fault initiateAcc(ExecContext *, trace::InstRecord *) const override;
Fault completeAcc(PacketPtr, ExecContext *,
- Trace::InstRecord *) const override;
+ trace::InstRecord *) const override;
};
}};
@@ -660,10 +660,10 @@
uint32_t _dest, uint32_t _dest2,
uint32_t _base, bool _add, int32_t _imm);
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
- Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
+ Fault initiateAcc(ExecContext *, trace::InstRecord *) const override;
Fault completeAcc(PacketPtr, ExecContext *,
- Trace::InstRecord *) const override;
+ trace::InstRecord *) const override;
};
}};
@@ -682,10 +682,10 @@
uint32_t _result, uint32_t _dest, uint32_t _dest2,
uint32_t _base, bool _add, int32_t _imm);
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
- Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
+ Fault initiateAcc(ExecContext *, trace::InstRecord *) const override;
Fault completeAcc(PacketPtr, ExecContext *,
- Trace::InstRecord *) const override;
+ trace::InstRecord *) const override;
};
}};
@@ -703,10 +703,10 @@
%(class_name)s(ExtMachInst machInst,
uint32_t _dest, uint32_t _base, bool _add, int32_t _imm);
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
- Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
+ Fault initiateAcc(ExecContext *, trace::InstRecord *) const override;
Fault completeAcc(PacketPtr, ExecContext *,
- Trace::InstRecord *) const override;
+ trace::InstRecord *) const override;
void
annotateFault(ArmISA::ArmFault *fault) override
@@ -731,10 +731,10 @@
uint32_t _result, uint32_t _dest, uint32_t _base,
bool _add, int32_t _imm);
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
- Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
+ Fault initiateAcc(ExecContext *, trace::InstRecord *) const override;
Fault completeAcc(PacketPtr, ExecContext *,
- Trace::InstRecord *) const override;
+ trace::InstRecord *) const override;
};
}};
@@ -755,10 +755,10 @@
int32_t _shiftAmt, uint32_t _shiftType,
uint32_t _index);
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
- Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
+ Fault initiateAcc(ExecContext *, trace::InstRecord *) const override;
Fault completeAcc(PacketPtr, ExecContext *,
- Trace::InstRecord *) const override;
+ trace::InstRecord *) const override;
};
}};
@@ -778,10 +778,10 @@
int32_t _shiftAmt, uint32_t _shiftType,
uint32_t _index);
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
- Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
+ Fault initiateAcc(ExecContext *, trace::InstRecord *) const override;
Fault completeAcc(PacketPtr, ExecContext *,
- Trace::InstRecord *) const override;
+ trace::InstRecord *) const override;
void
annotateFault(ArmISA::ArmFault *fault) override
@@ -808,10 +808,10 @@
int32_t _shiftAmt, uint32_t _shiftType,
uint32_t _index);
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
- Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
+ Fault initiateAcc(ExecContext *, trace::InstRecord *) const override;
Fault completeAcc(PacketPtr, ExecContext *,
- Trace::InstRecord *) const override;
+ trace::InstRecord *) const override;
};
}};
@@ -831,10 +831,10 @@
int32_t _shiftAmt, uint32_t _shiftType,
uint32_t _index);
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
- Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
+ Fault initiateAcc(ExecContext *, trace::InstRecord *) const override;
Fault completeAcc(PacketPtr, ExecContext *,
- Trace::InstRecord *) const override;
+ trace::InstRecord *) const override;
void
annotateFault(ArmISA::ArmFault *fault) override
@@ -858,10 +858,10 @@
%(class_name)s(ExtMachInst machInst,
uint32_t _dest, uint32_t _base, bool _add, int32_t _imm);
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
- Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
+ Fault initiateAcc(ExecContext *, trace::InstRecord *) const override;
Fault completeAcc(PacketPtr, ExecContext *,
- Trace::InstRecord *) const override;
+ trace::InstRecord *) const override;
void
annotateFault(ArmISA::ArmFault *fault) override
diff --git a/src/arch/arm/isa/templates/mem64.isa b/src/arch/arm/isa/templates/mem64.isa
index 1421b60..991e97c 100644
--- a/src/arch/arm/isa/templates/mem64.isa
+++ b/src/arch/arm/isa/templates/mem64.isa
@@ -47,7 +47,7 @@
def template Load64Execute {{
Fault
%(class_name)s::execute(ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
@@ -72,7 +72,7 @@
def template Load64FpExecute {{
Fault
%(class_name)s::execute(ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
@@ -97,7 +97,7 @@
def template Store64Execute {{
Fault
%(class_name)s::execute(ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
@@ -126,7 +126,7 @@
def template Store64InitiateAcc {{
Fault
%(class_name)s::initiateAcc(ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
@@ -151,7 +151,7 @@
def template StoreEx64Execute {{
Fault
%(class_name)s::execute(ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
@@ -185,7 +185,7 @@
def template StoreEx64InitiateAcc {{
Fault
%(class_name)s::initiateAcc(ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
@@ -210,7 +210,7 @@
def template Load64InitiateAcc {{
Fault
%(class_name)s::initiateAcc(ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
@@ -230,7 +230,7 @@
def template Load64CompleteAcc {{
Fault
%(class_name)s::completeAcc(PacketPtr pkt, ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
Fault fault = NoFault;
@@ -255,7 +255,7 @@
def template Store64CompleteAcc {{
Fault
%(class_name)s::completeAcc(PacketPtr pkt, ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
return NoFault;
}
@@ -264,7 +264,7 @@
def template StoreEx64CompleteAcc {{
Fault
%(class_name)s::completeAcc(PacketPtr pkt, ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
Fault fault = NoFault;
@@ -293,10 +293,10 @@
%(class_name)s(ExtMachInst machInst, RegIndex _base,
MiscRegIndex _dest);
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
- Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
+ Fault initiateAcc(ExecContext *, trace::InstRecord *) const override;
Fault completeAcc(PacketPtr, ExecContext *,
- Trace::InstRecord *) const override;
+ trace::InstRecord *) const override;
void
annotateFault(ArmISA::ArmFault *fault) override
@@ -321,7 +321,7 @@
def template DCStore64Execute {{
Fault
%(class_name)s::execute(ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
@@ -352,7 +352,7 @@
def template DCStore64InitiateAcc {{
Fault
%(class_name)s::initiateAcc(ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
@@ -387,10 +387,10 @@
%(class_name)s(ExtMachInst machInst,
RegIndex _dest, RegIndex _base, int64_t _imm);
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
- Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
+ Fault initiateAcc(ExecContext *, trace::InstRecord *) const override;
Fault completeAcc(PacketPtr, ExecContext *,
- Trace::InstRecord *) const override;
+ trace::InstRecord *) const override;
void
annotateFault(ArmISA::ArmFault *fault) override
@@ -413,10 +413,10 @@
bool noAlloc = false, bool exclusive = false,
bool acrel = false);
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
- Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
+ Fault initiateAcc(ExecContext *, trace::InstRecord *) const override;
Fault completeAcc(PacketPtr, ExecContext *,
- Trace::InstRecord *) const override;
+ trace::InstRecord *) const override;
void
annotateFault(ArmISA::ArmFault *fault) override
@@ -439,10 +439,10 @@
int64_t _imm = 0, bool noAlloc = false, bool exclusive = false,
bool acrel = false);
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
- Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
+ Fault initiateAcc(ExecContext *, trace::InstRecord *) const override;
Fault completeAcc(PacketPtr, ExecContext *,
- Trace::InstRecord *) const override;
+ trace::InstRecord *) const override;
void
annotateFault(ArmISA::ArmFault *fault) override
@@ -467,10 +467,10 @@
RegIndex _result, RegIndex _dest, RegIndex _dest2,
RegIndex _base, int64_t _imm = 0);
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
- Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
+ Fault initiateAcc(ExecContext *, trace::InstRecord *) const override;
Fault completeAcc(PacketPtr, ExecContext *,
- Trace::InstRecord *) const override;
+ trace::InstRecord *) const override;
};
}};
@@ -487,10 +487,10 @@
RegIndex _dest, RegIndex _base, RegIndex _offset,
ArmExtendType _type, uint32_t _shiftAmt);
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
- Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
+ Fault initiateAcc(ExecContext *, trace::InstRecord *) const override;
Fault completeAcc(PacketPtr, ExecContext *,
- Trace::InstRecord *) const override;
+ trace::InstRecord *) const override;
void
annotateFault(ArmISA::ArmFault *fault) override
@@ -514,10 +514,10 @@
bool noAlloc = false, bool exclusive = false,
bool acrel = false);
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
- Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
+ Fault initiateAcc(ExecContext *, trace::InstRecord *) const override;
Fault completeAcc(PacketPtr, ExecContext *,
- Trace::InstRecord *) const override;
+ trace::InstRecord *) const override;
void
annotateFault(ArmISA::ArmFault *fault) override
@@ -538,10 +538,10 @@
%(class_name)s(ExtMachInst machInst, RegIndex _dest,
RegIndex _base);
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
- Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
+ Fault initiateAcc(ExecContext *, trace::InstRecord *) const override;
Fault completeAcc(PacketPtr, ExecContext *,
- Trace::InstRecord *) const override;
+ trace::InstRecord *) const override;
void
annotateFault(ArmISA::ArmFault *fault) override
@@ -562,10 +562,10 @@
%(class_name)s(ExtMachInst machInst, RegIndex _dest,
RegIndex _base, RegIndex _result);
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
- Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
+ Fault initiateAcc(ExecContext *, trace::InstRecord *) const override;
Fault completeAcc(PacketPtr, ExecContext *,
- Trace::InstRecord *) const override;
+ trace::InstRecord *) const override;
void
annotateFault(ArmISA::ArmFault *fault) override
@@ -585,10 +585,10 @@
/// Constructor.
%(class_name)s(ExtMachInst machInst, RegIndex _dest, int64_t _imm);
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
- Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
+ Fault initiateAcc(ExecContext *, trace::InstRecord *) const override;
Fault completeAcc(PacketPtr, ExecContext *,
- Trace::InstRecord *) const override;
+ trace::InstRecord *) const override;
void
annotateFault(ArmISA::ArmFault *fault) override
@@ -610,10 +610,10 @@
bool noAlloc = false, bool exclusive = false,
bool acrel = false);
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
- Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
+ Fault initiateAcc(ExecContext *, trace::InstRecord *) const override;
Fault completeAcc(PacketPtr, ExecContext *,
- Trace::InstRecord *) const override;
+ trace::InstRecord *) const override;
void
annotateFault(ArmISA::ArmFault *fault) override
@@ -782,7 +782,7 @@
def template AmoOpExecute {{
Fault
%(class_name)s::execute(ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
Addr EA;
@@ -812,7 +812,7 @@
def template AmoOpInitiateAcc {{
Fault
%(class_name)s::initiateAcc(ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
Addr EA;
@@ -834,7 +834,7 @@
def template AmoOpCompleteAcc {{
Fault
%(class_name)s::completeAcc(PacketPtr pkt, ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
%(op_decl)s;
%(op_rd)s;
@@ -862,10 +862,10 @@
%(class_name)s(ExtMachInst machInst, RegIndex _dest,
RegIndex _base, RegIndex _result);
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
- Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
+ Fault initiateAcc(ExecContext *, trace::InstRecord *) const override;
Fault completeAcc(PacketPtr, ExecContext *,
- Trace::InstRecord *) const override;
+ trace::InstRecord *) const override;
void
annotateFault(ArmISA::ArmFault *fault) override
@@ -901,10 +901,10 @@
%(class_name)s(ExtMachInst machInst, RegIndex _dest,
RegIndex _base, RegIndex _result);
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
- Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
+ Fault initiateAcc(ExecContext *, trace::InstRecord *) const override;
Fault completeAcc(PacketPtr, ExecContext *,
- Trace::InstRecord *) const override;
+ trace::InstRecord *) const override;
void
annotateFault(ArmISA::ArmFault *fault) override
diff --git a/src/arch/arm/isa/templates/misc.isa b/src/arch/arm/isa/templates/misc.isa
index 36c78f6..3bb3afa 100644
--- a/src/arch/arm/isa/templates/misc.isa
+++ b/src/arch/arm/isa/templates/misc.isa
@@ -44,7 +44,7 @@
public:
// Constructor
%(class_name)s(ExtMachInst machInst, RegIndex _dest);
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -76,7 +76,7 @@
// Constructor
%(class_name)s(ExtMachInst machInst, RegIndex _dest,
uint8_t _sysM, bool _r);
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -109,7 +109,7 @@
// Constructor
%(class_name)s(ExtMachInst machInst, RegIndex _op1,
uint8_t _sysM, bool _r);
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -138,7 +138,7 @@
public:
// Constructor
%(class_name)s(ExtMachInst machInst, RegIndex _op1, uint8_t mask);
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -166,7 +166,7 @@
public:
// Constructor
%(class_name)s(ExtMachInst machInst, uint32_t imm, uint8_t mask);
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -195,7 +195,7 @@
// Constructor
%(class_name)s(ExtMachInst machInst, MiscRegIndex _op1,
RegIndex _dest, RegIndex _dest2, uint32_t imm);
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -226,7 +226,7 @@
// Constructor
%(class_name)s(ExtMachInst machInst, RegIndex _op1, RegIndex _op2,
MiscRegIndex _dest, uint32_t imm);
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -256,7 +256,7 @@
public:
// Constructor
%(class_name)s(ExtMachInst machInst, uint64_t _imm);
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -283,7 +283,7 @@
public:
// Constructor
%(class_name)s(ExtMachInst machInst, RegIndex _dest, uint64_t _imm);
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -311,7 +311,7 @@
public:
// Constructor
%(class_name)s(ExtMachInst machInst, RegIndex _dest, RegIndex _op1);
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -340,7 +340,7 @@
// Constructor
%(class_name)s(ExtMachInst machInst, RegIndex _dest,
RegIndex _op1, RegIndex _op2, uint64_t _imm);
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -371,7 +371,7 @@
// Constructor
%(class_name)s(ExtMachInst machInst, RegIndex _dest,
RegIndex _op1, RegIndex _op2, RegIndex _op3);
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -402,7 +402,7 @@
// Constructor
%(class_name)s(ExtMachInst machInst, RegIndex _dest,
RegIndex _op1, RegIndex _op2);
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -432,7 +432,7 @@
// Constructor
%(class_name)s(ExtMachInst machInst, RegIndex _dest, RegIndex _op1,
uint64_t _imm);
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -462,7 +462,7 @@
// Constructor
%(class_name)s(ExtMachInst machInst, MiscRegIndex _dest, RegIndex _op1,
uint64_t _imm);
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -492,7 +492,7 @@
// Constructor
%(class_name)s(ExtMachInst machInst, RegIndex _dest, MiscRegIndex _op1,
uint64_t _imm);
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -522,7 +522,7 @@
// Constructor
%(class_name)s(ExtMachInst machInst, RegIndex _dest,
uint64_t _imm1, uint64_t _imm2);
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -552,7 +552,7 @@
// Constructor
%(class_name)s(ExtMachInst machInst, RegIndex _dest, RegIndex _op1,
uint64_t _imm1, uint64_t _imm2);
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -583,7 +583,7 @@
// Constructor
%(class_name)s(ExtMachInst machInst, RegIndex _dest,
uint64_t _imm, RegIndex _op1);
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -614,7 +614,7 @@
%(class_name)s(ExtMachInst machInst, RegIndex _dest, uint64_t _imm,
RegIndex _op1, int32_t _shiftAmt,
ArmShiftType _shiftType);
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -646,17 +646,17 @@
// Constructor
%(class_name)s(ExtMachInst machInst, MiscRegIndex _dest,
RegIndex _op1, uint64_t _imm);
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
- Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
+ Fault initiateAcc(ExecContext *, trace::InstRecord *) const override;
Fault completeAcc(PacketPtr, ExecContext *,
- Trace::InstRecord *) const override;
+ trace::InstRecord *) const override;
};
}};
def template Mcr15Execute {{
Fault
%(class_name)s::execute(ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
@@ -687,7 +687,7 @@
def template Mcr15InitiateAcc {{
Fault
%(class_name)s::initiateAcc(ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
@@ -718,7 +718,7 @@
def template Mcr15CompleteAcc {{
Fault
%(class_name)s::completeAcc(PacketPtr pkt, ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
return NoFault;
}
diff --git a/src/arch/arm/isa/templates/misc64.isa b/src/arch/arm/isa/templates/misc64.isa
index e1fb76e..af6b4c6 100644
--- a/src/arch/arm/isa/templates/misc64.isa
+++ b/src/arch/arm/isa/templates/misc64.isa
@@ -45,7 +45,7 @@
// Constructor
%(class_name)s(ExtMachInst machInst,uint64_t _imm);
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -69,7 +69,7 @@
%(class_name)s(ExtMachInst machInst,
RegIndex _dest, RegIndex _op1,
uint64_t _imm1, uint64_t _imm2);
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -95,7 +95,7 @@
// Constructor
%(class_name)s(ExtMachInst machInst, RegIndex _dest, RegIndex _op1,
RegIndex _op2, uint64_t _imm);
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -121,7 +121,7 @@
// Constructor
%(class_name)s(ExtMachInst machInst, MiscRegIndex _dest, uint64_t _imm);
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -146,7 +146,7 @@
%(class_name)s(ExtMachInst machInst, MiscRegIndex _dest,
RegIndex _op1);
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -172,7 +172,7 @@
%(class_name)s(ExtMachInst machInst, RegIndex _dest,
MiscRegIndex _op1);
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -197,7 +197,7 @@
public:
// Constructor
%(class_name)s(ExtMachInst machInst, RegIndex _dest);
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -221,7 +221,7 @@
// Constructor
%(class_name)s(ExtMachInst machInst, RegIndex _dest);
- Fault execute(ExecContext *, Trace::InstRecord *) const;
+ Fault execute(ExecContext *, trace::InstRecord *) const;
};
}};
@@ -246,10 +246,10 @@
%(class_name)s(ExtMachInst machInst, MiscRegIndex _dest,
RegIndex _op1, bool dvm_enabled);
- Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+ Fault initiateAcc(ExecContext *, trace::InstRecord *) const override;
Fault completeAcc(PacketPtr, ExecContext *,
- Trace::InstRecord *) const override;
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -266,10 +266,10 @@
public:
/// Constructor.
%(class_name)s(ExtMachInst machInst, bool dvm_enabled);
- Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+ Fault initiateAcc(ExecContext *, trace::InstRecord *) const override;
Fault completeAcc(PacketPtr, ExecContext *,
- Trace::InstRecord *) const override;
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -306,7 +306,7 @@
def template DvmInitiateAcc {{
Fault
%(class_name)s::initiateAcc(ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
Fault fault = NoFault;
@@ -326,7 +326,7 @@
def template DvmCompleteAcc {{
Fault
%(class_name)s::completeAcc(PacketPtr pkt, ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
return NoFault;
}
diff --git a/src/arch/arm/isa/templates/mult.isa b/src/arch/arm/isa/templates/mult.isa
index e94cc93..7a68c8a 100644
--- a/src/arch/arm/isa/templates/mult.isa
+++ b/src/arch/arm/isa/templates/mult.isa
@@ -45,7 +45,7 @@
// Constructor
%(class_name)s(ExtMachInst machInst, RegIndex _reg0,
RegIndex _reg1, RegIndex _reg2);
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -76,7 +76,7 @@
%(class_name)s(ExtMachInst machInst,
RegIndex _reg0, RegIndex _reg1,
RegIndex _reg2, RegIndex _reg3);
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
diff --git a/src/arch/arm/isa/templates/neon.isa b/src/arch/arm/isa/templates/neon.isa
index 2a64424..682061c 100644
--- a/src/arch/arm/isa/templates/neon.isa
+++ b/src/arch/arm/isa/templates/neon.isa
@@ -74,7 +74,7 @@
}
}
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -105,7 +105,7 @@
}
}
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -135,7 +135,7 @@
}
}
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -163,7 +163,7 @@
}
}
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -193,14 +193,14 @@
}
}
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
def template NeonExecDeclare {{
template
Fault %(class_name)s<%(targs)s>::execute(
- ExecContext *, Trace::InstRecord *) const;
+ ExecContext *, trace::InstRecord *) const;
}};
output header {{
@@ -233,7 +233,7 @@
template <class Element>
Fault
%(class_name)s<Element>::execute(ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
Fault fault = NoFault;
%(op_decl)s;
@@ -285,7 +285,7 @@
template <class Element>
Fault
%(class_name)s<Element>::execute(ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
typedef typename bigger_type_t<Element>::type BigElement;
Fault fault = NoFault;
diff --git a/src/arch/arm/isa/templates/neon64.isa b/src/arch/arm/isa/templates/neon64.isa
index f315f1e..b8fb6db 100644
--- a/src/arch/arm/isa/templates/neon64.isa
+++ b/src/arch/arm/isa/templates/neon64.isa
@@ -60,7 +60,7 @@
%(constructor)s;
}
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -86,7 +86,7 @@
%(constructor)s;
}
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -109,7 +109,7 @@
%(constructor)s;
}
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -134,7 +134,7 @@
%(constructor)s;
}
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -160,7 +160,7 @@
%(constructor)s;
}
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -183,21 +183,21 @@
%(constructor)s;
}
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
def template NeonXExecDeclare {{
template
Fault %(class_name)s<%(targs)s>::execute(
- ExecContext *, Trace::InstRecord *) const;
+ ExecContext *, trace::InstRecord *) const;
}};
def template NeonXEqualRegOpExecute {{
template <class Element>
Fault
%(class_name)s<Element>::execute(ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
Fault fault = NoFault;
%(op_decl)s;
@@ -232,7 +232,7 @@
template <class Element>
Fault
%(class_name)s<Element>::execute(ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
typedef typename bigger_type_t<Element>::type BigElement;
Fault fault = NoFault;
@@ -299,17 +299,17 @@
%(constructor)s;
}
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
- Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
+ Fault initiateAcc(ExecContext *, trace::InstRecord *) const override;
Fault completeAcc(PacketPtr, ExecContext *,
- Trace::InstRecord *) const override;
+ trace::InstRecord *) const override;
};
}};
def template NeonLoadExecute64 {{
Fault
%(class_name)s::execute(
- ExecContext *xc, Trace::InstRecord *traceData) const
+ ExecContext *xc, trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
@@ -340,7 +340,7 @@
def template NeonLoadInitiateAcc64 {{
Fault
%(class_name)s::initiateAcc(
- ExecContext *xc, Trace::InstRecord *traceData) const
+ ExecContext *xc, trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
@@ -362,7 +362,7 @@
def template NeonLoadCompleteAcc64 {{
Fault
%(class_name)s::completeAcc(
- PacketPtr pkt, ExecContext *xc, Trace::InstRecord *traceData) const
+ PacketPtr pkt, ExecContext *xc, trace::InstRecord *traceData) const
{
Fault fault = NoFault;
@@ -388,7 +388,7 @@
def template NeonStoreExecute64 {{
Fault
%(class_name)s::execute(
- ExecContext *xc, Trace::InstRecord *traceData) const
+ ExecContext *xc, trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
@@ -422,7 +422,7 @@
def template NeonStoreInitiateAcc64 {{
Fault
%(class_name)s::initiateAcc(
- ExecContext *xc, Trace::InstRecord *traceData) const
+ ExecContext *xc, trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
@@ -450,7 +450,7 @@
def template NeonStoreCompleteAcc64 {{
Fault
%(class_name)s::completeAcc(
- PacketPtr pkt, ExecContext *xc, Trace::InstRecord *traceData) const
+ PacketPtr pkt, ExecContext *xc, trace::InstRecord *traceData) const
{
return NoFault;
}
@@ -533,7 +533,7 @@
%(constructor)s;
}
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -556,14 +556,14 @@
%(constructor)s;
}
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
def template MicroNeonMixExecute64 {{
Fault
%(class_name)s::execute(
- ExecContext *xc, Trace::InstRecord *traceData) const
+ ExecContext *xc, trace::InstRecord *traceData) const
{
Fault fault = NoFault;
uint64_t resTemp = 0;
diff --git a/src/arch/arm/isa/templates/pred.isa b/src/arch/arm/isa/templates/pred.isa
index 3acc724..176d03a 100644
--- a/src/arch/arm/isa/templates/pred.isa
+++ b/src/arch/arm/isa/templates/pred.isa
@@ -58,7 +58,7 @@
// Constructor
%(class_name)s(ExtMachInst machInst, RegIndex _dest,
RegIndex _op1, uint32_t _imm, bool _rotC=true);
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -99,7 +99,7 @@
%(class_name)s(ExtMachInst machInst, RegIndex _dest,
RegIndex _op1, RegIndex _op2,
int32_t _shiftAmt, ArmShiftType _shiftType);
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -146,7 +146,7 @@
%(class_name)s(ExtMachInst machInst, RegIndex _dest,
RegIndex _op1, RegIndex _op2, RegIndex _shift,
ArmShiftType _shiftType);
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -171,7 +171,7 @@
def template PredOpExecute {{
Fault
%(class_name)s::execute(
- ExecContext *xc, Trace::InstRecord *traceData) const
+ ExecContext *xc, trace::InstRecord *traceData) const
{
Fault fault = NoFault;
uint64_t resTemp = 0;
@@ -195,7 +195,7 @@
def template QuiescePredOpExecute {{
Fault
%(class_name)s::execute(
- ExecContext *xc, Trace::InstRecord *traceData) const
+ ExecContext *xc, trace::InstRecord *traceData) const
{
Fault fault = NoFault;
uint64_t resTemp = 0;
@@ -221,7 +221,7 @@
def template QuiescePredOpExecuteWithFixup {{
Fault
%(class_name)s::execute(
- ExecContext *xc, Trace::InstRecord *traceData) const
+ ExecContext *xc, trace::InstRecord *traceData) const
{
Fault fault = NoFault;
uint64_t resTemp = 0;
diff --git a/src/arch/arm/isa/templates/sve.isa b/src/arch/arm/isa/templates/sve.isa
index b52a189..87316f1 100644
--- a/src/arch/arm/isa/templates/sve.isa
+++ b/src/arch/arm/isa/templates/sve.isa
@@ -69,7 +69,7 @@
%(constructor)s;
}
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -95,7 +95,7 @@
%(constructor)s;
}
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -119,7 +119,7 @@
%(constructor)s;
}
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -144,7 +144,7 @@
%(constructor)s;
}
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -168,7 +168,7 @@
%(constructor)s;
}
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -195,7 +195,7 @@
%(constructor)s;
}
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -221,7 +221,7 @@
%(constructor)s;
}
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -247,7 +247,7 @@
%(constructor)s;
}
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -273,7 +273,7 @@
%(constructor)s;
}
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -300,7 +300,7 @@
%(constructor)s;
}
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -326,7 +326,7 @@
%(constructor)s;
}
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -352,7 +352,7 @@
%(constructor)s;
}
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -379,7 +379,7 @@
%(constructor)s;
}
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -405,7 +405,7 @@
%(constructor)s;
}
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -431,7 +431,7 @@
%(constructor)s;
}
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -457,7 +457,7 @@
%(constructor)s;
}
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -483,7 +483,7 @@
%(constructor)s;
}
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -509,7 +509,7 @@
%(constructor)s;
}
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -535,7 +535,7 @@
%(constructor)s;
}
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -564,7 +564,7 @@
%(constructor)s;
}
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -590,7 +590,7 @@
%(constructor)s;
}
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -616,7 +616,7 @@
%(constructor)s;
}
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -642,7 +642,7 @@
%(constructor)s;
}
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -668,7 +668,7 @@
%(constructor)s;
}
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -692,7 +692,7 @@
%(constructor)s;
}
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -717,7 +717,7 @@
%(constructor)s;
}
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -742,7 +742,7 @@
%(constructor)s;
}
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -769,7 +769,7 @@
%(constructor)s;
}
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -794,7 +794,7 @@
%(constructor)s;
}
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -817,7 +817,7 @@
%(constructor)s;
}
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -842,7 +842,7 @@
%(constructor)s;
}
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -868,7 +868,7 @@
esize = sizeof(Element);
}
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -888,7 +888,7 @@
%(constructor)s;
}
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -910,7 +910,7 @@
%(constructor)s;
}
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -936,7 +936,7 @@
scalar_width = (sizeof(Element) == 8) ? 64 : 32;
}
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -962,7 +962,7 @@
%(constructor)s;
}
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -980,7 +980,7 @@
%(constructor)s;
}
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -998,7 +998,7 @@
%(constructor)s;
}
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -1016,7 +1016,7 @@
%(constructor)s;
}
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -1034,7 +1034,7 @@
%(constructor)s;
}
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -1052,7 +1052,7 @@
%(constructor)s;
}
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -1081,7 +1081,7 @@
esize = sizeof(Element);
}
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -1110,7 +1110,7 @@
esize = sizeof(Element);
}
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -1137,7 +1137,7 @@
%(constructor)s;
}
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -1164,7 +1164,7 @@
%(constructor)s;
}
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -1172,7 +1172,7 @@
template <class SElement, class DElement>
Fault
%(class_name)s<SElement, DElement>::execute(ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
Fault fault = NoFault;
%(op_decl)s;
@@ -1190,7 +1190,7 @@
def template SveNonTemplatedOpExecute {{
Fault
%(class_name)s::execute(ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
Fault fault = NoFault;
%(op_decl)s;
@@ -1209,7 +1209,7 @@
template <class Element>
Fault
%(class_name)s<Element>::execute(ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
Fault fault = NoFault;
%(op_decl)s;
@@ -1227,5 +1227,5 @@
def template SveOpExecDeclare {{
template
Fault %(class_name)s<%(targs)s>::execute(
- ExecContext *, Trace::InstRecord *) const;
+ ExecContext *, trace::InstRecord *) const;
}};
diff --git a/src/arch/arm/isa/templates/sve_mem.isa b/src/arch/arm/isa/templates/sve_mem.isa
index 5eb8975..aa131f8 100644
--- a/src/arch/arm/isa/templates/sve_mem.isa
+++ b/src/arch/arm/isa/templates/sve_mem.isa
@@ -54,10 +54,10 @@
%(constructor)s;
}
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
- Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
+ Fault initiateAcc(ExecContext *, trace::InstRecord *) const override;
Fault completeAcc(PacketPtr, ExecContext *,
- Trace::InstRecord *) const override;
+ trace::InstRecord *) const override;
void
annotateFault(ArmISA::ArmFault *fault) override
@@ -88,10 +88,10 @@
%(constructor)s;
}
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
- Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
+ Fault initiateAcc(ExecContext *, trace::InstRecord *) const override;
Fault completeAcc(PacketPtr, ExecContext *,
- Trace::InstRecord *) const override;
+ trace::InstRecord *) const override;
void
annotateFault(ArmISA::ArmFault *fault) override
@@ -122,10 +122,10 @@
%(constructor)s;
}
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
- Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
+ Fault initiateAcc(ExecContext *, trace::InstRecord *) const override;
Fault completeAcc(PacketPtr, ExecContext *,
- Trace::InstRecord *) const override;
+ trace::InstRecord *) const override;
void
annotateFault(ArmISA::ArmFault *fault) override
@@ -138,22 +138,22 @@
def template SveContigMemExecDeclare {{
template
Fault %(class_name)s%(tpl_args)s::execute(ExecContext *,
- Trace::InstRecord *) const;
+ trace::InstRecord *) const;
template
Fault %(class_name)s%(tpl_args)s::initiateAcc(ExecContext *,
- Trace::InstRecord *) const;
+ trace::InstRecord *) const;
template
Fault %(class_name)s%(tpl_args)s::completeAcc(PacketPtr,
- ExecContext *, Trace::InstRecord *) const;
+ ExecContext *, trace::InstRecord *) const;
}};
def template SveContigLoadExecute {{
%(tpl_header)s
Fault
%(class_name)s%(tpl_args)s::execute(ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
@@ -188,7 +188,7 @@
%(tpl_header)s
Fault
%(class_name)s%(tpl_args)s::initiateAcc(ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
@@ -215,7 +215,7 @@
%(tpl_header)s
Fault
%(class_name)s%(tpl_args)s::completeAcc(PacketPtr pkt,
- ExecContext *xc, Trace::InstRecord *traceData) const
+ ExecContext *xc, trace::InstRecord *traceData) const
{
[[maybe_unused]] bool aarch64 = true;
unsigned eCount =
@@ -243,7 +243,7 @@
%(tpl_header)s
Fault
%(class_name)s%(tpl_args)s::execute(ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
@@ -281,7 +281,7 @@
%(tpl_header)s
Fault
%(class_name)s%(tpl_args)s::initiateAcc(ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
@@ -315,7 +315,7 @@
%(tpl_header)s
Fault
%(class_name)s%(tpl_args)s::completeAcc(PacketPtr pkt,
- ExecContext *xc, Trace::InstRecord *traceData) const
+ ExecContext *xc, trace::InstRecord *traceData) const
{
return NoFault;
}
@@ -325,7 +325,7 @@
%(tpl_header)s
Fault
%(class_name)s%(tpl_args)s::execute(ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
@@ -357,7 +357,7 @@
%(tpl_header)s
Fault
%(class_name)s%(tpl_args)s::initiateAcc(ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
@@ -383,7 +383,7 @@
%(tpl_header)s
Fault
%(class_name)s%(tpl_args)s::completeAcc(PacketPtr pkt,
- ExecContext *xc, Trace::InstRecord *traceData) const
+ ExecContext *xc, trace::InstRecord *traceData) const
{
Fault fault = NoFault;
[[maybe_unused]] bool aarch64 = true;
@@ -454,10 +454,10 @@
}
}
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
- Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
+ Fault initiateAcc(ExecContext *, trace::InstRecord *) const override;
Fault completeAcc(PacketPtr, ExecContext *,
- Trace::InstRecord *) const override;
+ trace::InstRecord *) const override;
void
annotateFault(ArmISA::ArmFault *fault) override
@@ -542,10 +542,10 @@
}
}
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
- Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
+ Fault initiateAcc(ExecContext *, trace::InstRecord *) const override;
Fault completeAcc(PacketPtr, ExecContext *,
- Trace::InstRecord *) const override;
+ trace::InstRecord *) const override;
void
annotateFault(ArmISA::ArmFault *fault) override
@@ -581,7 +581,7 @@
%(tpl_header)s
Fault
%(class_name)s%(tpl_args)s::execute(ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
@@ -630,7 +630,7 @@
%(tpl_header)s
Fault
%(class_name)s%(tpl_args)s::initiateAcc(ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
@@ -673,7 +673,7 @@
%(tpl_header)s
Fault
%(class_name)s%(tpl_args)s::completeAcc(PacketPtr pkt,
- ExecContext *xc, Trace::InstRecord *traceData) const
+ ExecContext *xc, trace::InstRecord *traceData) const
{
[[maybe_unused]] bool aarch64 = true;
@@ -698,7 +698,7 @@
%(tpl_header)s
Fault
%(class_name)s%(tpl_args)s::execute(ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
@@ -729,7 +729,7 @@
%(tpl_header)s
Fault
%(class_name)s%(tpl_args)s::initiateAcc(ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
@@ -758,7 +758,7 @@
%(tpl_header)s
Fault
%(class_name)s%(tpl_args)s::completeAcc(PacketPtr pkt,
- ExecContext *xc, Trace::InstRecord *traceData) const
+ ExecContext *xc, trace::InstRecord *traceData) const
{
return NoFault;
}
@@ -786,7 +786,7 @@
%(constructor)s;
}
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
std::string
generateDisassembly(Addr pc,
@@ -804,7 +804,7 @@
%(tpl_header)s
Fault
%(class_name)s%(tpl_args)s::execute(ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
[[maybe_unused]] bool aarch64 = true;
@@ -847,7 +847,7 @@
%(constructor)s;
}
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
std::string
generateDisassembly(Addr pc,
@@ -864,7 +864,7 @@
def template SveGatherLoadCpySrcVecMicroopExecute {{
Fault
SveGatherLoadCpySrcVecMicroop::execute(ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
Fault fault = NoFault;
%(op_decl)s;
@@ -916,10 +916,10 @@
baseIsSP = isSP(_base);
}
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
- Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
+ Fault initiateAcc(ExecContext *, trace::InstRecord *) const override;
Fault completeAcc(PacketPtr, ExecContext *,
- Trace::InstRecord *) const override;
+ trace::InstRecord *) const override;
void
annotateFault(ArmISA::ArmFault *fault) override
@@ -970,22 +970,22 @@
def template SveStructMemExecDeclare {{
template
Fault %(class_name)s<%(targs)s>::execute(ExecContext *,
- Trace::InstRecord *) const;
+ trace::InstRecord *) const;
template
Fault %(class_name)s<%(targs)s>::initiateAcc(ExecContext *,
- Trace::InstRecord *) const;
+ trace::InstRecord *) const;
template
Fault %(class_name)s<%(targs)s>::completeAcc(PacketPtr,
- ExecContext *, Trace::InstRecord *) const;
+ ExecContext *, trace::InstRecord *) const;
}};
def template SveStructLoadExecute {{
template <class Element>
Fault
%(class_name)s<Element>::execute(ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
@@ -1019,7 +1019,7 @@
template <class Element>
Fault
%(class_name)s<Element>::initiateAcc(ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
@@ -1046,7 +1046,7 @@
template <class Element>
Fault
%(class_name)s<Element>::completeAcc(PacketPtr pkt,
- ExecContext *xc, Trace::InstRecord *traceData) const
+ ExecContext *xc, trace::InstRecord *traceData) const
{
Fault fault = NoFault;
[[maybe_unused]] bool aarch64 = true;
@@ -1078,7 +1078,7 @@
template <class Element>
Fault
%(class_name)s<Element>::execute(ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
@@ -1116,7 +1116,7 @@
template <class Element>
Fault
%(class_name)s<Element>::initiateAcc(ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
@@ -1150,7 +1150,7 @@
template <class Element>
Fault
%(class_name)s<Element>::completeAcc(PacketPtr pkt,
- ExecContext *xc, Trace::InstRecord *traceData) const
+ ExecContext *xc, trace::InstRecord *traceData) const
{
return NoFault;
}
@@ -1193,10 +1193,10 @@
baseIsSP = isSP(_base);
}
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
- Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
+ Fault initiateAcc(ExecContext *, trace::InstRecord *) const override;
Fault completeAcc(PacketPtr, ExecContext *,
- Trace::InstRecord *) const override;
+ trace::InstRecord *) const override;
void
annotateFault(ArmISA::ArmFault *fault) override
@@ -1271,7 +1271,7 @@
%(constructor)s;
}
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
std::string
generateDisassembly(Addr pc,
@@ -1312,7 +1312,7 @@
%(constructor)s;
}
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
std::string
generateDisassembly(Addr pc,
@@ -1329,14 +1329,14 @@
def template SveIntrlvMicroopExecDeclare {{
template
Fault %(class_name)s<%(targs)s>::execute(
- ExecContext *, Trace::InstRecord *) const;
+ ExecContext *, trace::InstRecord *) const;
}};
def template SveIntrlvMicroopExecute {{
template <class Element>
Fault
%(class_name)s<Element>::execute(ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
Fault fault = NoFault;
%(op_decl)s;
diff --git a/src/arch/arm/isa/templates/vfp.isa b/src/arch/arm/isa/templates/vfp.isa
index 2f59f4f..40dfcac 100644
--- a/src/arch/arm/isa/templates/vfp.isa
+++ b/src/arch/arm/isa/templates/vfp.isa
@@ -106,7 +106,7 @@
%(class_name)s(ExtMachInst machInst,
RegIndex _dest, RegIndex _op1,
VfpMicroMode mode = VfpNotAMicroop);
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -137,7 +137,7 @@
// Constructor
%(class_name)s(ExtMachInst machInst, RegIndex _dest,
uint64_t _imm, VfpMicroMode mode = VfpNotAMicroop);
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -168,7 +168,7 @@
%(class_name)s(ExtMachInst machInst,
RegIndex _dest, RegIndex _op1,
uint64_t _imm, VfpMicroMode mode = VfpNotAMicroop);
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -202,7 +202,7 @@
%(class_name)s(ExtMachInst machInst,
RegIndex _dest, RegIndex _op1, RegIndex _op2,
VfpMicroMode mode = VfpNotAMicroop);
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -237,7 +237,7 @@
RegIndex _dest, RegIndex _op1, RegIndex _op2,
ConditionCode _cond,
VfpMicroMode mode = VfpNotAMicroop);
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
diff --git a/src/arch/arm/isa/templates/vfp64.isa b/src/arch/arm/isa/templates/vfp64.isa
index 883fd43..0d7a447 100644
--- a/src/arch/arm/isa/templates/vfp64.isa
+++ b/src/arch/arm/isa/templates/vfp64.isa
@@ -93,7 +93,7 @@
%(class_name)s(ExtMachInst machInst,
RegIndex _dest, RegIndex _op1, RegIndex _op2,
RegIndex _op3, VfpMicroMode mode=VfpNotAMicroop);
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
diff --git a/src/arch/arm/nativetrace.cc b/src/arch/arm/nativetrace.cc
index 7e105b7..1b8f286 100644
--- a/src/arch/arm/nativetrace.cc
+++ b/src/arch/arm/nativetrace.cc
@@ -55,7 +55,7 @@
using namespace ArmISA;
-namespace Trace {
+namespace trace {
[[maybe_unused]] static const char *regNames[] = {
"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
@@ -68,7 +68,7 @@
};
void
-Trace::ArmNativeTrace::ThreadState::update(NativeTrace *parent)
+ArmNativeTrace::ThreadState::update(NativeTrace *parent)
{
oldState = state[current];
current = (current + 1) % 2;
@@ -103,7 +103,7 @@
}
void
-Trace::ArmNativeTrace::ThreadState::update(ThreadContext *tc)
+ArmNativeTrace::ThreadState::update(ThreadContext *tc)
{
oldState = state[current];
current = (current + 1) % 2;
@@ -141,7 +141,7 @@
}
void
-Trace::ArmNativeTrace::check(NativeTraceRecord *record)
+ArmNativeTrace::check(NativeTraceRecord *record)
{
ThreadContext *tc = record->getThread();
// This area is read only on the target. It can't stop there to tell us
@@ -223,5 +223,5 @@
}
}
-} // namespace Trace
+} // namespace trace
} // namespace gem5
diff --git a/src/arch/arm/nativetrace.hh b/src/arch/arm/nativetrace.hh
index c5abd44..509567a 100644
--- a/src/arch/arm/nativetrace.hh
+++ b/src/arch/arm/nativetrace.hh
@@ -36,7 +36,7 @@
namespace gem5
{
-namespace Trace {
+namespace trace {
class ArmNativeTrace : public NativeTrace
{
@@ -110,7 +110,7 @@
void check(NativeTraceRecord *record);
};
-} // namespace Trace
+} // namespace trace
} // namespace gem5
#endif // __ARCH_ARM_NATIVETRACE_HH__
diff --git a/src/arch/arm/tracers/TarmacTrace.py b/src/arch/arm/tracers/TarmacTrace.py
index d592e52..0e87ec9 100644
--- a/src/arch/arm/tracers/TarmacTrace.py
+++ b/src/arch/arm/tracers/TarmacTrace.py
@@ -40,7 +40,7 @@
class TarmacParser(InstTracer):
type = "TarmacParser"
- cxx_class = "gem5::Trace::TarmacParser"
+ cxx_class = "gem5::trace::TarmacParser"
cxx_header = "arch/arm/tracers/tarmac_parser.hh"
path_to_trace = Param.String("tarmac.log", "path to TARMAC trace")
@@ -69,7 +69,7 @@
class TarmacTracer(InstTracer):
type = "TarmacTracer"
- cxx_class = "gem5::Trace::TarmacTracer"
+ cxx_class = "gem5::trace::TarmacTracer"
cxx_header = "arch/arm/tracers/tarmac_tracer.hh"
start_tick = Param.Tick(
diff --git a/src/arch/arm/tracers/tarmac_base.cc b/src/arch/arm/tracers/tarmac_base.cc
index c8a8619..99ed3bb 100644
--- a/src/arch/arm/tracers/tarmac_base.cc
+++ b/src/arch/arm/tracers/tarmac_base.cc
@@ -50,7 +50,7 @@
using namespace ArmISA;
-namespace Trace {
+namespace trace {
TarmacBaseRecord::TarmacBaseRecord(Tick _when, ThreadContext *_thread,
const StaticInstPtr _staticInst,
@@ -118,5 +118,5 @@
return isetstate;
}
-} // namespace Trace
+} // namespace trace
} // namespace gem5
diff --git a/src/arch/arm/tracers/tarmac_base.hh b/src/arch/arm/tracers/tarmac_base.hh
index 7948ee6..501eb1b 100644
--- a/src/arch/arm/tracers/tarmac_base.hh
+++ b/src/arch/arm/tracers/tarmac_base.hh
@@ -60,7 +60,7 @@
class ThreadContext;
-namespace Trace {
+namespace trace {
class TarmacBaseRecord : public InstRecord
{
@@ -147,7 +147,7 @@
};
-} // namespace Trace
+} // namespace trace
} // namespace gem5
#endif // __ARCH_ARM_TRACERS_TARMAC_BASE_HH__
diff --git a/src/arch/arm/tracers/tarmac_parser.cc b/src/arch/arm/tracers/tarmac_parser.cc
index 5ab3a0e..cb2d9e3 100644
--- a/src/arch/arm/tracers/tarmac_parser.cc
+++ b/src/arch/arm/tracers/tarmac_parser.cc
@@ -64,7 +64,7 @@
using namespace ArmISA;
-namespace Trace {
+namespace trace {
// TARMAC Parser static variables
const int TarmacParserRecord::MaxLineLength;
@@ -745,7 +745,7 @@
void
TarmacParserRecord::TarmacParserRecordEvent::process()
{
- std::ostream &outs = Trace::output();
+ std::ostream &outs = trace::output();
std::list<ParserRegEntry>::iterator it = destRegRecords.begin(),
end = destRegRecords.end();
@@ -934,7 +934,7 @@
TarmacParserRecord::printMismatchHeader(const StaticInstPtr staticInst,
const PCStateBase &pc)
{
- std::ostream &outs = Trace::output();
+ std::ostream &outs = trace::output();
outs << "\nMismatch between gem5 and TARMAC trace @ " << std::dec
<< curTick() << " ticks\n"
<< "[seq_num: " << std::dec << instRecord.seq_num
@@ -963,7 +963,7 @@
void
TarmacParserRecord::dump()
{
- std::ostream &outs = Trace::output();
+ std::ostream &outs = trace::output();
uint64_t written_data = 0;
unsigned mem_flags = 3 | ArmISA::MMU::AllowUnaligned;
@@ -1357,5 +1357,5 @@
}
}
-} // namespace Trace
+} // namespace trace
} // namespace gem5
diff --git a/src/arch/arm/tracers/tarmac_parser.hh b/src/arch/arm/tracers/tarmac_parser.hh
index 39cf5c3..41c4e78 100644
--- a/src/arch/arm/tracers/tarmac_parser.hh
+++ b/src/arch/arm/tracers/tarmac_parser.hh
@@ -62,7 +62,7 @@
namespace gem5
{
-namespace Trace {
+namespace trace {
class TarmacParserRecord : public TarmacBaseRecord
{
@@ -300,7 +300,7 @@
bool macroopInProgress;
};
-} // namespace Trace
+} // namespace trace
} // namespace gem5
#endif // __ARCH_ARM_TRACERS_TARMAC_PARSER_HH__
diff --git a/src/arch/arm/tracers/tarmac_record.cc b/src/arch/arm/tracers/tarmac_record.cc
index 811111d..9d56aa3 100644
--- a/src/arch/arm/tracers/tarmac_record.cc
+++ b/src/arch/arm/tracers/tarmac_record.cc
@@ -47,7 +47,7 @@
using namespace ArmISA;
-namespace Trace {
+namespace trace {
// TARMAC Instruction Record static variables
uint64_t TarmacTracerRecord::TraceInstEntry::instCount = 0;
@@ -374,7 +374,7 @@
void
TarmacTracerRecord::flushQueues(Queue& queue)
{
- std::ostream &outs = Trace::output();
+ std::ostream &outs = trace::output();
for (const auto &single_entry : queue) {
single_entry->print(outs);
@@ -446,5 +446,5 @@
values[Lo]); /* Register value */
}
-} // namespace Trace
+} // namespace trace
} // namespace gem5
diff --git a/src/arch/arm/tracers/tarmac_record.hh b/src/arch/arm/tracers/tarmac_record.hh
index 80ca3e2..009df5d 100644
--- a/src/arch/arm/tracers/tarmac_record.hh
+++ b/src/arch/arm/tracers/tarmac_record.hh
@@ -54,7 +54,7 @@
namespace gem5
{
-namespace Trace {
+namespace trace {
class TarmacContext;
@@ -258,7 +258,7 @@
TarmacTracer& tracer;
};
-} // namespace Trace
+} // namespace trace
} // namespace gem5
#endif // __ARCH_ARM_TRACERS_TARMAC_RECORD_HH__
diff --git a/src/arch/arm/tracers/tarmac_record_v8.cc b/src/arch/arm/tracers/tarmac_record_v8.cc
index c025969..29606c3 100644
--- a/src/arch/arm/tracers/tarmac_record_v8.cc
+++ b/src/arch/arm/tracers/tarmac_record_v8.cc
@@ -48,7 +48,7 @@
using namespace ArmISA;
-namespace Trace {
+namespace trace {
TarmacTracerRecordV8::TraceInstEntryV8::TraceInstEntryV8(
const TarmacContext& tarmCtx,
@@ -313,5 +313,5 @@
}
}
-} // namespace Trace
+} // namespace trace
} // namespace gem5
diff --git a/src/arch/arm/tracers/tarmac_record_v8.hh b/src/arch/arm/tracers/tarmac_record_v8.hh
index 7d318e3..ae972b0 100644
--- a/src/arch/arm/tracers/tarmac_record_v8.hh
+++ b/src/arch/arm/tracers/tarmac_record_v8.hh
@@ -48,7 +48,7 @@
namespace gem5
{
-namespace Trace {
+namespace trace {
/**
* TarmacTracer record for ARMv8 CPUs:
@@ -158,7 +158,7 @@
void addRegEntry(std::vector<RegPtr>& queue, const TarmacContext& ptr);
};
-} // namespace Trace
+} // namespace trace
} // namespace gem5
#endif // __ARCH_ARM_TRACERS_TARMAC_RECORD_V8_HH__
diff --git a/src/arch/arm/tracers/tarmac_tracer.cc b/src/arch/arm/tracers/tarmac_tracer.cc
index e017cc4..15f6abc 100644
--- a/src/arch/arm/tracers/tarmac_tracer.cc
+++ b/src/arch/arm/tracers/tarmac_tracer.cc
@@ -45,7 +45,7 @@
namespace gem5
{
-namespace Trace {
+namespace trace {
std::string
TarmacContext::tarmacCpuName() const
@@ -95,5 +95,5 @@
}
}
-} // namespace Trace
+} // namespace trace
} // namespace gem5
diff --git a/src/arch/arm/tracers/tarmac_tracer.hh b/src/arch/arm/tracers/tarmac_tracer.hh
index 29e82ff..7e7b409 100644
--- a/src/arch/arm/tracers/tarmac_tracer.hh
+++ b/src/arch/arm/tracers/tarmac_tracer.hh
@@ -55,7 +55,7 @@
class ThreadContext;
-namespace Trace {
+namespace trace {
/**
* This object type is encapsulating the informations needed by
@@ -129,7 +129,7 @@
std::vector<RegPtr> regQueue;
};
-} // namespace Trace
+} // namespace trace
} // namespace gem5
#endif // __ARCH_ARM_TRACERS_TARMAC_TRACER_HH__
diff --git a/src/arch/generic/memhelpers.hh b/src/arch/generic/memhelpers.hh
index b07a654..d5684a6 100644
--- a/src/arch/generic/memhelpers.hh
+++ b/src/arch/generic/memhelpers.hh
@@ -64,7 +64,7 @@
/// to determine the size of the access.
template <class XC, class MemT>
Fault
-initiateMemRead(XC *xc, Trace::InstRecord *traceData, Addr addr,
+initiateMemRead(XC *xc, trace::InstRecord *traceData, Addr addr,
MemT &mem, Request::Flags flags)
{
static const std::vector<bool> byte_enable(sizeof(MemT), true);
@@ -75,7 +75,7 @@
/// Extract the data returned from a timing mode read.
template <ByteOrder Order, class MemT>
void
-getMem(PacketPtr pkt, MemT &mem, Trace::InstRecord *traceData)
+getMem(PacketPtr pkt, MemT &mem, trace::InstRecord *traceData)
{
mem = pkt->get<MemT>(Order);
if (traceData)
@@ -84,14 +84,14 @@
template <class MemT>
void
-getMemLE(PacketPtr pkt, MemT &mem, Trace::InstRecord *traceData)
+getMemLE(PacketPtr pkt, MemT &mem, trace::InstRecord *traceData)
{
getMem<ByteOrder::little>(pkt, mem, traceData);
}
template <class MemT>
void
-getMemBE(PacketPtr pkt, MemT &mem, Trace::InstRecord *traceData)
+getMemBE(PacketPtr pkt, MemT &mem, trace::InstRecord *traceData)
{
getMem<ByteOrder::big>(pkt, mem, traceData);
}
@@ -109,7 +109,7 @@
/// Read from memory in atomic mode.
template <ByteOrder Order, class XC, class MemT>
Fault
-readMemAtomic(XC *xc, Trace::InstRecord *traceData, Addr addr, MemT &mem,
+readMemAtomic(XC *xc, trace::InstRecord *traceData, Addr addr, MemT &mem,
Request::Flags flags)
{
memset(&mem, 0, sizeof(mem));
@@ -126,7 +126,7 @@
template <class XC, class MemT>
Fault
-readMemAtomicLE(XC *xc, Trace::InstRecord *traceData, Addr addr, MemT &mem,
+readMemAtomicLE(XC *xc, trace::InstRecord *traceData, Addr addr, MemT &mem,
Request::Flags flags)
{
return readMemAtomic<ByteOrder::little>(
@@ -135,7 +135,7 @@
template <class XC, class MemT>
Fault
-readMemAtomicBE(XC *xc, Trace::InstRecord *traceData, Addr addr, MemT &mem,
+readMemAtomicBE(XC *xc, trace::InstRecord *traceData, Addr addr, MemT &mem,
Request::Flags flags)
{
return readMemAtomic<ByteOrder::big>(xc, traceData, addr, mem, flags);
@@ -153,7 +153,7 @@
template <ByteOrder Order, class XC, class MemT>
Fault
-writeMemTiming(XC *xc, Trace::InstRecord *traceData, MemT mem, Addr addr,
+writeMemTiming(XC *xc, trace::InstRecord *traceData, MemT mem, Addr addr,
Request::Flags flags, uint64_t *res)
{
if (traceData) {
@@ -167,7 +167,7 @@
template <class XC, class MemT>
Fault
-writeMemTimingLE(XC *xc, Trace::InstRecord *traceData, MemT mem, Addr addr,
+writeMemTimingLE(XC *xc, trace::InstRecord *traceData, MemT mem, Addr addr,
Request::Flags flags, uint64_t *res)
{
return writeMemTiming<ByteOrder::little>(
@@ -176,7 +176,7 @@
template <class XC, class MemT>
Fault
-writeMemTimingBE(XC *xc, Trace::InstRecord *traceData, MemT mem, Addr addr,
+writeMemTimingBE(XC *xc, trace::InstRecord *traceData, MemT mem, Addr addr,
Request::Flags flags, uint64_t *res)
{
return writeMemTiming<ByteOrder::big>(
@@ -195,7 +195,7 @@
template <ByteOrder Order, class XC, class MemT>
Fault
-writeMemAtomic(XC *xc, Trace::InstRecord *traceData, const MemT &mem,
+writeMemAtomic(XC *xc, trace::InstRecord *traceData, const MemT &mem,
Addr addr, Request::Flags flags, uint64_t *res)
{
if (traceData) {
@@ -216,7 +216,7 @@
template <class XC, class MemT>
Fault
-writeMemAtomicLE(XC *xc, Trace::InstRecord *traceData, const MemT &mem,
+writeMemAtomicLE(XC *xc, trace::InstRecord *traceData, const MemT &mem,
Addr addr, Request::Flags flags, uint64_t *res)
{
return writeMemAtomic<ByteOrder::little>(
@@ -225,7 +225,7 @@
template <class XC, class MemT>
Fault
-writeMemAtomicBE(XC *xc, Trace::InstRecord *traceData, const MemT &mem,
+writeMemAtomicBE(XC *xc, trace::InstRecord *traceData, const MemT &mem,
Addr addr, Request::Flags flags, uint64_t *res)
{
return writeMemAtomic<ByteOrder::big>(
@@ -235,7 +235,7 @@
/// Do atomic read-modify-write (AMO) in atomic mode
template <ByteOrder Order, class XC, class MemT>
Fault
-amoMemAtomic(XC *xc, Trace::InstRecord *traceData, MemT &mem, Addr addr,
+amoMemAtomic(XC *xc, trace::InstRecord *traceData, MemT &mem, Addr addr,
Request::Flags flags, AtomicOpFunctor *_amo_op)
{
assert(_amo_op);
@@ -257,7 +257,7 @@
template <class XC, class MemT>
Fault
-amoMemAtomicLE(XC *xc, Trace::InstRecord *traceData, MemT &mem, Addr addr,
+amoMemAtomicLE(XC *xc, trace::InstRecord *traceData, MemT &mem, Addr addr,
Request::Flags flags, AtomicOpFunctor *_amo_op)
{
return amoMemAtomic<ByteOrder::little>(
@@ -266,7 +266,7 @@
template <class XC, class MemT>
Fault
-amoMemAtomicBE(XC *xc, Trace::InstRecord *traceData, MemT &mem, Addr addr,
+amoMemAtomicBE(XC *xc, trace::InstRecord *traceData, MemT &mem, Addr addr,
Request::Flags flags, AtomicOpFunctor *_amo_op)
{
return amoMemAtomic<ByteOrder::big>(
@@ -276,7 +276,7 @@
/// Do atomic read-modify-wrote (AMO) in timing mode
template <class XC, class MemT>
Fault
-initiateMemAMO(XC *xc, Trace::InstRecord *traceData, Addr addr, MemT& mem,
+initiateMemAMO(XC *xc, trace::InstRecord *traceData, Addr addr, MemT& mem,
Request::Flags flags, AtomicOpFunctor *_amo_op)
{
assert(_amo_op);
diff --git a/src/arch/mips/isa/formats/basic.isa b/src/arch/mips/isa/formats/basic.isa
index 765dae2..8bb90d7 100644
--- a/src/arch/mips/isa/formats/basic.isa
+++ b/src/arch/mips/isa/formats/basic.isa
@@ -41,7 +41,7 @@
/// Constructor.
%(class_name)s(MachInst machInst);
Fault execute(ExecContext *,
- Trace::InstRecord *) const override;
+ trace::InstRecord *) const override;
};
}};
@@ -59,7 +59,7 @@
// Basic instruction class execute method template.
def template BasicExecute {{
Fault %(class_name)s::execute(
- ExecContext *xc, Trace::InstRecord *traceData) const
+ ExecContext *xc, trace::InstRecord *traceData) const
{
Fault fault = NoFault;
diff --git a/src/arch/mips/isa/formats/control.isa b/src/arch/mips/isa/formats/control.isa
index 8bad976..ea321db 100644
--- a/src/arch/mips/isa/formats/control.isa
+++ b/src/arch/mips/isa/formats/control.isa
@@ -64,7 +64,7 @@
// Basic instruction class execute method template.
def template CP0Execute {{
Fault %(class_name)s::execute(
- ExecContext *xc, Trace::InstRecord *traceData) const
+ ExecContext *xc, trace::InstRecord *traceData) const
{
Fault fault = NoFault;
%(op_decl)s;
@@ -86,7 +86,7 @@
def template CP1Execute {{
Fault %(class_name)s::execute(
- ExecContext *xc, Trace::InstRecord *traceData) const
+ ExecContext *xc, trace::InstRecord *traceData) const
{
Fault fault = NoFault;
%(op_decl)s;
@@ -108,7 +108,7 @@
// Basic instruction class execute method template.
def template ControlTLBExecute {{
Fault %(class_name)s::execute(
- ExecContext *xc, Trace::InstRecord *traceData) const
+ ExecContext *xc, trace::InstRecord *traceData) const
{
Fault fault = NoFault;
%(op_decl)s;
diff --git a/src/arch/mips/isa/formats/dsp.isa b/src/arch/mips/isa/formats/dsp.isa
index 431cc98..847251f 100644
--- a/src/arch/mips/isa/formats/dsp.isa
+++ b/src/arch/mips/isa/formats/dsp.isa
@@ -61,7 +61,7 @@
// Dsp instruction class execute method template.
def template DspExecute {{
Fault %(class_name)s::execute(
- ExecContext *xc, Trace::InstRecord *traceData) const
+ ExecContext *xc, trace::InstRecord *traceData) const
{
Fault fault = NoFault;
@@ -95,7 +95,7 @@
// DspHiLo instruction class execute method template.
def template DspHiLoExecute {{
Fault %(class_name)s::execute(
- ExecContext *xc, Trace::InstRecord *traceData) const
+ ExecContext *xc, trace::InstRecord *traceData) const
{
Fault fault = NoFault;
diff --git a/src/arch/mips/isa/formats/fp.isa b/src/arch/mips/isa/formats/fp.isa
index ccf4462..267972c 100644
--- a/src/arch/mips/isa/formats/fp.isa
+++ b/src/arch/mips/isa/formats/fp.isa
@@ -98,7 +98,7 @@
template <class T>
bool
fpNanOperands(FPOp *inst, ExecContext *xc, const T &src_type,
- Trace::InstRecord *traceData)
+ trace::InstRecord *traceData)
{
uint64_t mips_nan = 0;
assert(sizeof(T) == 4);
@@ -119,7 +119,7 @@
template <class T>
bool
fpInvalidOp(FPOp *inst, ExecContext *cpu, const T dest_val,
- Trace::InstRecord *traceData)
+ trace::InstRecord *traceData)
{
uint64_t mips_nan = 0;
T src_op = dest_val;
@@ -162,7 +162,7 @@
def template FloatingPointExecute {{
Fault %(class_name)s::execute(
- ExecContext *xc, Trace::InstRecord *traceData) const
+ ExecContext *xc, trace::InstRecord *traceData) const
{
Fault fault = NoFault;
diff --git a/src/arch/mips/isa/formats/int.isa b/src/arch/mips/isa/formats/int.isa
index f030696..11d4ade 100644
--- a/src/arch/mips/isa/formats/int.isa
+++ b/src/arch/mips/isa/formats/int.isa
@@ -109,7 +109,7 @@
def template HiLoExecute {{
Fault
%(class_name)s::execute(
- ExecContext *xc, Trace::InstRecord *traceData) const
+ ExecContext *xc, trace::InstRecord *traceData) const
{
Fault fault = NoFault;
@@ -129,7 +129,7 @@
def template HiLoRsSelExecute {{
Fault
%(class_name)s::execute(
- ExecContext *xc, Trace::InstRecord *traceData) const
+ ExecContext *xc, trace::InstRecord *traceData) const
{
Fault fault = NoFault;
@@ -153,7 +153,7 @@
def template HiLoRdSelExecute {{
Fault
%(class_name)s::execute(
- ExecContext *xc, Trace::InstRecord *traceData) const
+ ExecContext *xc, trace::InstRecord *traceData) const
{
Fault fault = NoFault;
diff --git a/src/arch/mips/isa/formats/mem.isa b/src/arch/mips/isa/formats/mem.isa
index 67973e1..1041500 100644
--- a/src/arch/mips/isa/formats/mem.isa
+++ b/src/arch/mips/isa/formats/mem.isa
@@ -136,10 +136,10 @@
/// Constructor.
%(class_name)s(ExtMachInst machInst);
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
- Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
+ Fault initiateAcc(ExecContext *, trace::InstRecord *) const override;
Fault completeAcc(Packet *, ExecContext *,
- Trace::InstRecord *) const override;
+ trace::InstRecord *) const override;
};
}};
@@ -155,7 +155,7 @@
def template LoadExecute {{
Fault %(class_name)s::execute(ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
@@ -187,7 +187,7 @@
def template LoadInitiateAcc {{
Fault %(class_name)s::initiateAcc(ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
@@ -213,7 +213,7 @@
def template LoadCompleteAcc {{
Fault %(class_name)s::completeAcc(Packet *pkt, ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
Fault fault = NoFault;
@@ -243,7 +243,7 @@
def template StoreExecute {{
Fault %(class_name)s::execute(ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
@@ -277,7 +277,7 @@
def template StoreFPExecute {{
Fault %(class_name)s::execute(ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
@@ -312,7 +312,7 @@
def template StoreCondExecute {{
Fault %(class_name)s::execute(ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
@@ -346,7 +346,7 @@
def template StoreInitiateAcc {{
Fault %(class_name)s::initiateAcc(ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
@@ -373,7 +373,7 @@
def template StoreCompleteAcc {{
Fault %(class_name)s::completeAcc(Packet *pkt,
ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
return NoFault;
}
@@ -382,7 +382,7 @@
def template StoreCondCompleteAcc {{
Fault %(class_name)s::completeAcc(Packet *pkt,
ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
Fault fault = NoFault;
@@ -405,7 +405,7 @@
def template MiscExecute {{
Fault %(class_name)s::execute(ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
[[maybe_unused]] Addr EA = 0;
Fault fault = NoFault;
@@ -425,7 +425,7 @@
def template MiscInitiateAcc {{
Fault %(class_name)s::initiateAcc(ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
panic("Misc instruction does not support split access method!");
return NoFault;
@@ -435,7 +435,7 @@
def template MiscCompleteAcc {{
Fault %(class_name)s::completeAcc(Packet *pkt, ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
panic("Misc instruction does not support split access method!");
diff --git a/src/arch/mips/isa/formats/mt.isa b/src/arch/mips/isa/formats/mt.isa
index f08b1a8..1ded627 100644
--- a/src/arch/mips/isa/formats/mt.isa
+++ b/src/arch/mips/isa/formats/mt.isa
@@ -107,7 +107,7 @@
def template ThreadRegisterExecute {{
Fault %(class_name)s::execute(
- ExecContext *xc, Trace::InstRecord *traceData) const
+ ExecContext *xc, trace::InstRecord *traceData) const
{
Fault fault = NoFault;
[[maybe_unused]] int64_t data;
@@ -146,7 +146,7 @@
def template MTExecute{{
Fault %(class_name)s::execute(
- ExecContext *xc, Trace::InstRecord *traceData) const
+ ExecContext *xc, trace::InstRecord *traceData) const
{
Fault fault = NoFault;
%(op_decl)s;
diff --git a/src/arch/mips/isa/formats/noop.isa b/src/arch/mips/isa/formats/noop.isa
index 917148b..93807c5 100644
--- a/src/arch/mips/isa/formats/noop.isa
+++ b/src/arch/mips/isa/formats/noop.isa
@@ -54,7 +54,7 @@
std::string generateDisassembly(
Addr pc, const loader::SymbolTable *symtab) const override;
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -80,7 +80,7 @@
output exec {{
Fault
- Nop::execute(ExecContext *, Trace::InstRecord *) const
+ Nop::execute(ExecContext *, trace::InstRecord *) const
{
return NoFault;
}
diff --git a/src/arch/mips/isa/formats/tlbop.isa b/src/arch/mips/isa/formats/tlbop.isa
index a8d5076..ad6372a 100644
--- a/src/arch/mips/isa/formats/tlbop.isa
+++ b/src/arch/mips/isa/formats/tlbop.isa
@@ -56,7 +56,7 @@
def template TlbOpExecute {{
Fault %(class_name)s::execute(
- ExecContext *xc, Trace::InstRecord *traceData) const
+ ExecContext *xc, trace::InstRecord *traceData) const
{
//Write the resulting state to the execution context
%(op_wb)s;
diff --git a/src/arch/mips/isa/formats/trap.isa b/src/arch/mips/isa/formats/trap.isa
index 8b353ac..634b3c0 100644
--- a/src/arch/mips/isa/formats/trap.isa
+++ b/src/arch/mips/isa/formats/trap.isa
@@ -75,7 +75,7 @@
def template TrapExecute {{
// Edit This Template When Traps Are Implemented
Fault %(class_name)s::execute(
- ExecContext *xc, Trace::InstRecord *traceData) const
+ ExecContext *xc, trace::InstRecord *traceData) const
{
//Write the resulting state to the execution context
%(op_wb)s;
diff --git a/src/arch/mips/isa/formats/unimp.isa b/src/arch/mips/isa/formats/unimp.isa
index 6b4aaba..198e20b 100644
--- a/src/arch/mips/isa/formats/unimp.isa
+++ b/src/arch/mips/isa/formats/unimp.isa
@@ -51,7 +51,7 @@
flags[IsNonSpeculative] = true;
}
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
std::string generateDisassembly(
Addr pc, const loader::SymbolTable *symtab) const override;
@@ -68,7 +68,7 @@
flags[IsNonSpeculative] = true;
}
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
std::string generateDisassembly(
Addr pc, const loader::SymbolTable *symtab) const override;
@@ -85,7 +85,7 @@
flags[IsNonSpeculative] = true;
}
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
std::string generateDisassembly(
Addr pc, const loader::SymbolTable *symtab) const override;
@@ -102,7 +102,7 @@
flags[IsNonSpeculative] = true;
}
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
std::string generateDisassembly(
Addr pc, const loader::SymbolTable *symtab) const override;
@@ -133,7 +133,7 @@
flags[IsNonSpeculative] = true;
}
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
std::string generateDisassembly(
Addr pc, const loader::SymbolTable *symtab) const override;
@@ -179,7 +179,7 @@
output exec {{
Fault
FailUnimplemented::execute(ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
panic("attempt to execute unimplemented instruction '%s' "
"(inst 0x%08x, opcode 0x%x, binary:%s)", mnemonic, machInst, OPCODE,
@@ -189,7 +189,7 @@
Fault
CP0Unimplemented::execute(ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
if (FullSystem) {
if (!isCoprocessorEnabled(xc, 0))
@@ -206,7 +206,7 @@
Fault
CP1Unimplemented::execute(ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
if (FullSystem) {
if (!isCoprocessorEnabled(xc, 1))
@@ -223,7 +223,7 @@
Fault
CP2Unimplemented::execute(ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
if (FullSystem) {
if (!isCoprocessorEnabled(xc, 2))
@@ -240,7 +240,7 @@
Fault
WarnUnimplemented::execute(ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
if (!warned) {
warn("\tinstruction '%s' unimplemented\n", mnemonic);
diff --git a/src/arch/mips/isa/formats/unknown.isa b/src/arch/mips/isa/formats/unknown.isa
index c243ecd..8d3ccdf 100644
--- a/src/arch/mips/isa/formats/unknown.isa
+++ b/src/arch/mips/isa/formats/unknown.isa
@@ -49,7 +49,7 @@
flags[IsNonSpeculative] = true;
}
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
std::string generateDisassembly(
Addr pc, const loader::SymbolTable *symtab) const override;
@@ -68,7 +68,7 @@
output exec {{
Fault
- Unknown::execute(ExecContext *xc, Trace::InstRecord *traceData) const
+ Unknown::execute(ExecContext *xc, trace::InstRecord *traceData) const
{
return std::make_shared<ReservedInstructionFault>();
}
diff --git a/src/arch/power/isa/formats/basic.isa b/src/arch/power/isa/formats/basic.isa
index 20d380f..056c77e 100644
--- a/src/arch/power/isa/formats/basic.isa
+++ b/src/arch/power/isa/formats/basic.isa
@@ -39,7 +39,7 @@
public:
/// Constructor.
%(class_name)s(ExtMachInst machInst);
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -57,7 +57,7 @@
// Basic instruction class execute method template.
def template BasicExecute {{
Fault %(class_name)s::execute(
- ExecContext *xc, Trace::InstRecord *traceData) const
+ ExecContext *xc, trace::InstRecord *traceData) const
{
Fault fault = NoFault;
diff --git a/src/arch/power/isa/formats/mem.isa b/src/arch/power/isa/formats/mem.isa
index 97b4f81..a58f0e4 100644
--- a/src/arch/power/isa/formats/mem.isa
+++ b/src/arch/power/isa/formats/mem.isa
@@ -45,10 +45,10 @@
/// Constructor.
%(class_name)s(ExtMachInst machInst);
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
- Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
+ Fault initiateAcc(ExecContext *, trace::InstRecord *) const override;
Fault completeAcc(PacketPtr, ExecContext *,
- Trace::InstRecord *) const override;
+ trace::InstRecord *) const override;
};
}};
@@ -65,7 +65,7 @@
def template LoadExecute {{
Fault %(class_name)s::execute(ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
@@ -94,7 +94,7 @@
def template LoadInitiateAcc {{
Fault %(class_name)s::initiateAcc(ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
@@ -115,7 +115,7 @@
def template LoadCompleteAcc {{
Fault %(class_name)s::completeAcc(PacketPtr pkt,
ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
[[maybe_unused]] Addr EA;
Fault fault = NoFault;
@@ -146,7 +146,7 @@
def template StoreExecute {{
Fault %(class_name)s::execute(ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
@@ -180,7 +180,7 @@
def template StoreInitiateAcc {{
Fault %(class_name)s::initiateAcc(ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
Addr EA;
Fault fault = NoFault;
@@ -209,7 +209,7 @@
def template StoreCompleteAcc {{
Fault %(class_name)s::completeAcc(PacketPtr pkt, ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
[[maybe_unused]] Addr EA;
Fault fault = NoFault;
diff --git a/src/arch/power/isa/formats/misc.isa b/src/arch/power/isa/formats/misc.isa
index 877ac63..cca1252 100644
--- a/src/arch/power/isa/formats/misc.isa
+++ b/src/arch/power/isa/formats/misc.isa
@@ -33,7 +33,7 @@
def template MiscOpExecute {{
Fault %(class_name)s::execute(
- ExecContext *xc, Trace::InstRecord *traceData) const
+ ExecContext *xc, trace::InstRecord *traceData) const
{
Fault fault = NoFault;
%(op_decl)s;
diff --git a/src/arch/power/isa/formats/unimp.isa b/src/arch/power/isa/formats/unimp.isa
index e7d1d06..9e1e460 100644
--- a/src/arch/power/isa/formats/unimp.isa
+++ b/src/arch/power/isa/formats/unimp.isa
@@ -53,7 +53,7 @@
flags[IsNonSpeculative] = true;
}
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
std::string generateDisassembly(
Addr pc, const loader::SymbolTable *symtab) const override;
@@ -84,7 +84,7 @@
flags[IsNonSpeculative] = true;
}
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
std::string generateDisassembly(
Addr pc, const loader::SymbolTable *symtab) const override;
@@ -110,7 +110,7 @@
output exec {{
Fault
FailUnimplemented::execute(ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
panic("attempt to execute unimplemented instruction '%s' "
"(inst 0x%08x, opcode 0x%x, binary:%s)", mnemonic, machInst, PO,
@@ -120,7 +120,7 @@
Fault
WarnUnimplemented::execute(ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
if (!warned) {
warn("\tinstruction '%s' unimplemented\n", mnemonic);
diff --git a/src/arch/power/isa/formats/unknown.isa b/src/arch/power/isa/formats/unknown.isa
index 0c879aa..85dacc5 100644
--- a/src/arch/power/isa/formats/unknown.isa
+++ b/src/arch/power/isa/formats/unknown.isa
@@ -51,7 +51,7 @@
flags[IsNonSpeculative] = true;
}
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
std::string generateDisassembly(
Addr pc, const loader::SymbolTable *symtab) const override;
@@ -70,7 +70,7 @@
output exec {{
Fault
- Unknown::execute(ExecContext *xc, Trace::InstRecord *traceData) const
+ Unknown::execute(ExecContext *xc, trace::InstRecord *traceData) const
{
inform("attempt to execute unknown instruction at %s"
"(inst 0x%08x, opcode 0x%x, binary: %s)",
diff --git a/src/arch/riscv/insts/amo.cc b/src/arch/riscv/insts/amo.cc
index 4502fb1..d845c91 100644
--- a/src/arch/riscv/insts/amo.cc
+++ b/src/arch/riscv/insts/amo.cc
@@ -54,7 +54,7 @@
}
Fault MemFenceMicro::execute(ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
return NoFault;
}
diff --git a/src/arch/riscv/insts/amo.hh b/src/arch/riscv/insts/amo.hh
index 9c73c1f..0d64b07 100644
--- a/src/arch/riscv/insts/amo.hh
+++ b/src/arch/riscv/insts/amo.hh
@@ -52,7 +52,7 @@
protected:
using RiscvMicroInst::RiscvMicroInst;
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
std::string generateDisassembly(
Addr pc, const loader::SymbolTable *symtab) const override;
};
diff --git a/src/arch/riscv/insts/static_inst.hh b/src/arch/riscv/insts/static_inst.hh
index 7394fe2..bccecf2 100644
--- a/src/arch/riscv/insts/static_inst.hh
+++ b/src/arch/riscv/insts/static_inst.hh
@@ -116,20 +116,20 @@
}
Fault
- initiateAcc(ExecContext *xc, Trace::InstRecord *traceData) const override
+ initiateAcc(ExecContext *xc, trace::InstRecord *traceData) const override
{
panic("Tried to execute a macroop directly!\n");
}
Fault
completeAcc(PacketPtr pkt, ExecContext *xc,
- Trace::InstRecord *traceData) const override
+ trace::InstRecord *traceData) const override
{
panic("Tried to execute a macroop directly!\n");
}
Fault
- execute(ExecContext *xc, Trace::InstRecord *traceData) const override
+ execute(ExecContext *xc, trace::InstRecord *traceData) const override
{
panic("Tried to execute a macroop directly!\n");
}
diff --git a/src/arch/riscv/insts/unknown.hh b/src/arch/riscv/insts/unknown.hh
index 30cec98..a271eb9 100644
--- a/src/arch/riscv/insts/unknown.hh
+++ b/src/arch/riscv/insts/unknown.hh
@@ -58,7 +58,7 @@
{}
Fault
- execute(ExecContext *, Trace::InstRecord *) const override
+ execute(ExecContext *, trace::InstRecord *) const override
{
return std::make_shared<UnknownInstFault>(machInst);
}
diff --git a/src/arch/riscv/isa/formats/amo.isa b/src/arch/riscv/isa/formats/amo.isa
index 0206872..6b22e8f 100644
--- a/src/arch/riscv/isa/formats/amo.isa
+++ b/src/arch/riscv/isa/formats/amo.isa
@@ -59,10 +59,10 @@
// Constructor
%(class_name)sRMW(ExtMachInst machInst, %(class_name)s *_p);
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
- Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
+ Fault initiateAcc(ExecContext *, trace::InstRecord *) const override;
Fault completeAcc(PacketPtr, ExecContext *,
- Trace::InstRecord *) const override;
+ trace::InstRecord *) const override;
};
}};
@@ -91,10 +91,10 @@
// Constructor
%(class_name)sMicro(ExtMachInst machInst, %(class_name)s *_p);
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
- Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
+ Fault initiateAcc(ExecContext *, trace::InstRecord *) const override;
Fault completeAcc(PacketPtr, ExecContext *,
- Trace::InstRecord *) const override;
+ trace::InstRecord *) const override;
};
}};
@@ -233,7 +233,7 @@
def template LoadReservedExecute {{
Fault
%(class_name)s::%(class_name)sMicro::execute(
- ExecContext *xc, Trace::InstRecord *traceData) const
+ ExecContext *xc, trace::InstRecord *traceData) const
{
Addr EA;
@@ -260,7 +260,7 @@
def template StoreCondExecute {{
Fault %(class_name)s::%(class_name)sMicro::execute(ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
Addr EA;
uint64_t result;
@@ -294,7 +294,7 @@
def template AtomicMemOpRMWExecute {{
Fault %(class_name)s::%(class_name)sRMW::execute(ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
Addr EA;
@@ -328,7 +328,7 @@
def template LoadReservedInitiateAcc {{
Fault
%(class_name)s::%(class_name)sMicro::initiateAcc(ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
Addr EA;
@@ -346,7 +346,7 @@
def template StoreCondInitiateAcc {{
Fault
%(class_name)s::%(class_name)sMicro::initiateAcc(ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
Addr EA;
@@ -374,7 +374,7 @@
def template AtomicMemOpRMWInitiateAcc {{
Fault
%(class_name)s::%(class_name)sRMW::initiateAcc(ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
Addr EA;
@@ -397,7 +397,7 @@
def template LoadReservedCompleteAcc {{
Fault
%(class_name)s::%(class_name)sMicro::completeAcc(PacketPtr pkt,
- ExecContext *xc, Trace::InstRecord *traceData) const
+ ExecContext *xc, trace::InstRecord *traceData) const
{
%(op_decl)s;
%(op_rd)s;
@@ -413,7 +413,7 @@
def template StoreCondCompleteAcc {{
Fault %(class_name)s::%(class_name)sMicro::completeAcc(Packet *pkt,
- ExecContext *xc, Trace::InstRecord *traceData) const
+ ExecContext *xc, trace::InstRecord *traceData) const
{
%(op_dest_decl)s;
@@ -430,7 +430,7 @@
def template AtomicMemOpRMWCompleteAcc {{
Fault %(class_name)s::%(class_name)sRMW::completeAcc(Packet *pkt,
- ExecContext *xc, Trace::InstRecord *traceData) const
+ ExecContext *xc, trace::InstRecord *traceData) const
{
%(op_decl)s;
%(op_rd)s;
diff --git a/src/arch/riscv/isa/formats/basic.isa b/src/arch/riscv/isa/formats/basic.isa
index 416b458..6dfeea8 100644
--- a/src/arch/riscv/isa/formats/basic.isa
+++ b/src/arch/riscv/isa/formats/basic.isa
@@ -40,7 +40,7 @@
public:
/// Constructor.
%(class_name)s(MachInst machInst);
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
using %(base_class)s::generateDisassembly;
};
}};
@@ -60,7 +60,7 @@
def template BasicExecute {{
Fault
%(class_name)s::execute(ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
%(op_decl)s;
%(op_rd)s;
diff --git a/src/arch/riscv/isa/formats/compressed.isa b/src/arch/riscv/isa/formats/compressed.isa
index a2da59d..6fe899b 100644
--- a/src/arch/riscv/isa/formats/compressed.isa
+++ b/src/arch/riscv/isa/formats/compressed.isa
@@ -126,7 +126,7 @@
public:
/// Constructor.
%(class_name)s(MachInst machInst);
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
std::string generateDisassembly(
Addr pc, const loader::SymbolTable *symtab) const override;
};
@@ -136,7 +136,7 @@
def template CBasicExecute {{
Fault
%(class_name)s::execute(ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
%(op_decl)s;
%(op_rd)s;
diff --git a/src/arch/riscv/isa/formats/fp.isa b/src/arch/riscv/isa/formats/fp.isa
index d015239..65e81cd 100644
--- a/src/arch/riscv/isa/formats/fp.isa
+++ b/src/arch/riscv/isa/formats/fp.isa
@@ -34,7 +34,7 @@
//
def template FloatExecute {{
Fault %(class_name)s::execute(ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
STATUS status = xc->readMiscReg(MISCREG_STATUS);
if (status.fs == FPUStatus::OFF)
diff --git a/src/arch/riscv/isa/formats/mem.isa b/src/arch/riscv/isa/formats/mem.isa
index a0e242e..fa33458 100644
--- a/src/arch/riscv/isa/formats/mem.isa
+++ b/src/arch/riscv/isa/formats/mem.isa
@@ -44,10 +44,10 @@
/// Constructor.
%(class_name)s(ExtMachInst machInst);
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
- Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
+ Fault initiateAcc(ExecContext *, trace::InstRecord *) const override;
Fault completeAcc(PacketPtr, ExecContext *,
- Trace::InstRecord *) const override;
+ trace::InstRecord *) const override;
};
}};
@@ -98,7 +98,7 @@
def template LoadExecute {{
Fault
%(class_name)s::execute(
- ExecContext *xc, Trace::InstRecord *traceData) const
+ ExecContext *xc, trace::InstRecord *traceData) const
{
Addr EA;
@@ -127,7 +127,7 @@
def template LoadInitiateAcc {{
Fault
%(class_name)s::initiateAcc(ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
Addr EA;
@@ -145,7 +145,7 @@
def template LoadCompleteAcc {{
Fault
%(class_name)s::completeAcc(PacketPtr pkt, ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
%(op_decl)s;
%(op_rd)s;
@@ -162,7 +162,7 @@
def template StoreExecute {{
Fault
%(class_name)s::execute(ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
Addr EA;
@@ -193,7 +193,7 @@
def template StoreInitiateAcc {{
Fault
%(class_name)s::initiateAcc(ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
Addr EA;
@@ -222,7 +222,7 @@
def template StoreCompleteAcc {{
Fault
%(class_name)s::completeAcc(PacketPtr pkt, ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
return NoFault;
}
diff --git a/src/arch/riscv/isa/formats/standard.isa b/src/arch/riscv/isa/formats/standard.isa
index 1b3f8c3..3cad5ed 100644
--- a/src/arch/riscv/isa/formats/standard.isa
+++ b/src/arch/riscv/isa/formats/standard.isa
@@ -45,7 +45,7 @@
public:
/// Constructor.
%(class_name)s(MachInst machInst);
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
std::string generateDisassembly(Addr pc,
const loader::SymbolTable *symtab) const override;
};
@@ -64,7 +64,7 @@
def template ImmExecute {{
Fault
%(class_name)s::execute(
- ExecContext *xc, Trace::InstRecord *traceData) const
+ ExecContext *xc, trace::InstRecord *traceData) const
{
%(op_decl)s;
%(op_rd)s;
@@ -90,7 +90,7 @@
def template CILuiExecute {{
Fault
%(class_name)s::execute(
- ExecContext *xc, Trace::InstRecord *traceData) const
+ ExecContext *xc, trace::InstRecord *traceData) const
{
%(op_decl)s;
%(op_rd)s;
@@ -118,7 +118,7 @@
def template FenceExecute {{
Fault
%(class_name)s::execute(
- ExecContext *xc, Trace::InstRecord *traceData) const
+ ExecContext *xc, trace::InstRecord *traceData) const
{
%(op_decl)s;
%(op_rd)s;
@@ -169,7 +169,7 @@
public:
/// Constructor.
%(class_name)s(MachInst machInst);
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
std::string
generateDisassembly(
@@ -185,7 +185,7 @@
def template BranchExecute {{
Fault
%(class_name)s::execute(ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
%(op_decl)s;
%(op_rd)s;
@@ -227,7 +227,7 @@
public:
/// Constructor.
%(class_name)s(MachInst machInst);
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
std::string
generateDisassembly(
@@ -286,7 +286,7 @@
def template JumpExecute {{
Fault
%(class_name)s::execute(
- ExecContext *xc, Trace::InstRecord *traceData) const
+ ExecContext *xc, trace::InstRecord *traceData) const
{
%(op_decl)s;
%(op_rd)s;
@@ -321,7 +321,7 @@
def template CSRExecute {{
Fault
%(class_name)s::execute(ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
// We assume a riscv instruction is always run with a riscv ISA.
auto isa = static_cast<RiscvISA::ISA*>(xc->tcBase()->getIsaPtr());
diff --git a/src/arch/sparc/SparcNativeTrace.py b/src/arch/sparc/SparcNativeTrace.py
index 3aeb5f3..0a93126 100644
--- a/src/arch/sparc/SparcNativeTrace.py
+++ b/src/arch/sparc/SparcNativeTrace.py
@@ -32,5 +32,5 @@
class SparcNativeTrace(NativeTrace):
type = "SparcNativeTrace"
- cxx_class = "gem5::Trace::SparcNativeTrace"
+ cxx_class = "gem5::trace::SparcNativeTrace"
cxx_header = "arch/sparc/nativetrace.hh"
diff --git a/src/arch/sparc/insts/micro.hh b/src/arch/sparc/insts/micro.hh
index 8526cae..fa3ab20 100644
--- a/src/arch/sparc/insts/micro.hh
+++ b/src/arch/sparc/insts/micro.hh
@@ -71,19 +71,19 @@
}
Fault
- execute(ExecContext *, Trace::InstRecord *) const override
+ execute(ExecContext *, trace::InstRecord *) const override
{
panic("Tried to execute a macroop directly!\n");
}
Fault
- initiateAcc(ExecContext *, Trace::InstRecord *) const override
+ initiateAcc(ExecContext *, trace::InstRecord *) const override
{
panic("Tried to execute a macroop directly!\n");
}
Fault
- completeAcc(PacketPtr, ExecContext *, Trace::InstRecord *) const override
+ completeAcc(PacketPtr, ExecContext *, trace::InstRecord *) const override
{
panic("Tried to execute a macroop directly!\n");
}
diff --git a/src/arch/sparc/insts/nop.cc b/src/arch/sparc/insts/nop.cc
index 0d2aa21..f95056c 100644
--- a/src/arch/sparc/insts/nop.cc
+++ b/src/arch/sparc/insts/nop.cc
@@ -48,7 +48,7 @@
}
Fault
- execute(ExecContext *xc, Trace::InstRecord *traceData) const
+ execute(ExecContext *xc, trace::InstRecord *traceData) const
{
return NoFault;
}
@@ -71,7 +71,7 @@
def template NopExecute {{
Fault %(class_name)s::execute(ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
// Nothing to see here, move along
return NoFault;
diff --git a/src/arch/sparc/insts/nop.hh b/src/arch/sparc/insts/nop.hh
index 0aad703..bcba61d 100644
--- a/src/arch/sparc/insts/nop.hh
+++ b/src/arch/sparc/insts/nop.hh
@@ -56,7 +56,7 @@
}
Fault
- execute(ExecContext *xc, Trace::InstRecord *traceData) const override
+ execute(ExecContext *xc, trace::InstRecord *traceData) const override
{
return NoFault;
}
diff --git a/src/arch/sparc/insts/unimp.hh b/src/arch/sparc/insts/unimp.hh
index e8694d9..9eda012 100644
--- a/src/arch/sparc/insts/unimp.hh
+++ b/src/arch/sparc/insts/unimp.hh
@@ -62,7 +62,7 @@
{}
Fault
- execute(ExecContext *xc, Trace::InstRecord *traceData) const override
+ execute(ExecContext *xc, trace::InstRecord *traceData) const override
{
return std::make_shared<GenericISA::M5PanicFault>(
"attempt to execute unimplemented instruction '%s' (inst %#08x)",
@@ -99,7 +99,7 @@
{}
Fault
- execute(ExecContext *xc, Trace::InstRecord *traceData) const override
+ execute(ExecContext *xc, trace::InstRecord *traceData) const override
{
if (!warned) {
return std::make_shared<GenericISA::M5WarnFault>(
diff --git a/src/arch/sparc/insts/unknown.hh b/src/arch/sparc/insts/unknown.hh
index 813acf1..f4bb143 100644
--- a/src/arch/sparc/insts/unknown.hh
+++ b/src/arch/sparc/insts/unknown.hh
@@ -50,7 +50,7 @@
{}
Fault
- execute(ExecContext *, Trace::InstRecord *) const override
+ execute(ExecContext *, trace::InstRecord *) const override
{
return std::make_shared<IllegalInstruction>();
}
diff --git a/src/arch/sparc/isa/formats/basic.isa b/src/arch/sparc/isa/formats/basic.isa
index 0d2346d..1386e6e 100644
--- a/src/arch/sparc/isa/formats/basic.isa
+++ b/src/arch/sparc/isa/formats/basic.isa
@@ -37,7 +37,7 @@
public:
// Constructor.
%(class_name)s(ExtMachInst machInst);
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -54,8 +54,8 @@
public:
// Constructor.
%(class_name)s(ExtMachInst machInst);
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
- GEM5_NO_INLINE Fault doFpOp(ExecContext *, Trace::InstRecord *) const;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
+ GEM5_NO_INLINE Fault doFpOp(ExecContext *, trace::InstRecord *) const;
};
}};
@@ -72,7 +72,7 @@
public:
// Constructor.
%(class_name)s(const char *mnemonic, ExtMachInst machInst);
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -100,7 +100,7 @@
def template BasicExecute {{
Fault
%(class_name)s::execute(ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
Fault fault = NoFault;
@@ -119,7 +119,7 @@
def template FpExecute {{
Fault
%(class_name)s::execute(ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
Fault fault = NoFault;
@@ -137,7 +137,7 @@
def template DoFpOpExecute {{
Fault
-%(class_name)s::doFpOp(ExecContext *xc, Trace::InstRecord *traceData) const
+%(class_name)s::doFpOp(ExecContext *xc, trace::InstRecord *traceData) const
{
Fault fault = NoFault;
%(op_decl)s;
diff --git a/src/arch/sparc/isa/formats/branch.isa b/src/arch/sparc/isa/formats/branch.isa
index c1d9d6a..bf7991b 100644
--- a/src/arch/sparc/isa/formats/branch.isa
+++ b/src/arch/sparc/isa/formats/branch.isa
@@ -31,7 +31,7 @@
def template JumpExecute {{
Fault %(class_name)s::execute(ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
// Attempt to execute the instruction
Fault fault = NoFault;
@@ -53,7 +53,7 @@
def template BranchExecute {{
Fault
%(class_name)s::execute(ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
// Attempt to execute the instruction
Fault fault = NoFault;
diff --git a/src/arch/sparc/isa/formats/integerop.isa b/src/arch/sparc/isa/formats/integerop.isa
index 39326e8..36c4803 100644
--- a/src/arch/sparc/isa/formats/integerop.isa
+++ b/src/arch/sparc/isa/formats/integerop.isa
@@ -40,7 +40,7 @@
def template IntOpExecute {{
Fault %(class_name)s::execute(ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
Fault fault = NoFault;
diff --git a/src/arch/sparc/isa/formats/mem/basicmem.isa b/src/arch/sparc/isa/formats/mem/basicmem.isa
index 14758d7..e2cefbc 100644
--- a/src/arch/sparc/isa/formats/mem/basicmem.isa
+++ b/src/arch/sparc/isa/formats/mem/basicmem.isa
@@ -45,11 +45,11 @@
/// Constructor.
%(class_name)s(ExtMachInst machInst);
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *,
- Trace::InstRecord *) const override;
+ trace::InstRecord *) const override;
Fault completeAcc(PacketPtr, ExecContext *,
- Trace::InstRecord *) const override;
+ trace::InstRecord *) const override;
};
}};
diff --git a/src/arch/sparc/isa/formats/mem/blockmem.isa b/src/arch/sparc/isa/formats/mem/blockmem.isa
index 3ae0820..9f5c427 100644
--- a/src/arch/sparc/isa/formats/mem/blockmem.isa
+++ b/src/arch/sparc/isa/formats/mem/blockmem.isa
@@ -61,10 +61,10 @@
public:
// Constructor
%(class_name)s_%(micro_pc)s(ExtMachInst machInst);
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
- Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
+ Fault initiateAcc(ExecContext *, trace::InstRecord *) const override;
Fault completeAcc(PacketPtr, ExecContext *,
- Trace::InstRecord *) const override;
+ trace::InstRecord *) const override;
};
}};
diff --git a/src/arch/sparc/isa/formats/mem/swap.isa b/src/arch/sparc/isa/formats/mem/swap.isa
index 5b617cd..6d83a2f 100644
--- a/src/arch/sparc/isa/formats/mem/swap.isa
+++ b/src/arch/sparc/isa/formats/mem/swap.isa
@@ -27,7 +27,7 @@
// This template provides the execute functions for a swap
def template SwapExecute {{
Fault %(class_name)s::execute(ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
Fault fault = NoFault;
// This is to support the conditional store in cas instructions.
@@ -65,7 +65,7 @@
def template SwapInitiateAcc {{
Fault %(class_name)s::initiateAcc(ExecContext * xc,
- Trace::InstRecord * traceData) const
+ trace::InstRecord * traceData) const
{
Fault fault = NoFault;
Addr EA;
@@ -93,7 +93,7 @@
def template SwapCompleteAcc {{
Fault %(class_name)s::completeAcc(PacketPtr pkt, ExecContext * xc,
- Trace::InstRecord * traceData) const
+ trace::InstRecord * traceData) const
{
Fault fault = NoFault;
%(op_decl)s;
diff --git a/src/arch/sparc/isa/formats/mem/util.isa b/src/arch/sparc/isa/formats/mem/util.isa
index 82387e2..1e5a55b 100644
--- a/src/arch/sparc/isa/formats/mem/util.isa
+++ b/src/arch/sparc/isa/formats/mem/util.isa
@@ -32,7 +32,7 @@
// This template provides the execute functions for a load
def template LoadExecute {{
Fault %(class_name)s::execute(ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
Fault fault = NoFault;
Addr EA;
@@ -59,7 +59,7 @@
def template LoadInitiateAcc {{
Fault %(class_name)s::initiateAcc(ExecContext * xc,
- Trace::InstRecord * traceData) const
+ trace::InstRecord * traceData) const
{
Fault fault = NoFault;
Addr EA;
@@ -78,7 +78,7 @@
def template LoadCompleteAcc {{
Fault %(class_name)s::completeAcc(PacketPtr pkt, ExecContext * xc,
- Trace::InstRecord * traceData) const
+ trace::InstRecord * traceData) const
{
Fault fault = NoFault;
%(op_decl)s;
@@ -95,7 +95,7 @@
// This template provides the execute functions for a store
def template StoreExecute {{
Fault %(class_name)s::execute(ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
Fault fault = NoFault;
// This is to support the conditional store in cas instructions.
@@ -126,7 +126,7 @@
def template StoreInitiateAcc {{
Fault %(class_name)s::initiateAcc(ExecContext * xc,
- Trace::InstRecord * traceData) const
+ trace::InstRecord * traceData) const
{
Fault fault = NoFault;
bool storeCond = true;
@@ -151,7 +151,7 @@
def template StoreCompleteAcc {{
Fault %(class_name)s::completeAcc(PacketPtr, ExecContext * xc,
- Trace::InstRecord * traceData) const
+ trace::InstRecord * traceData) const
{
return NoFault;
}
diff --git a/src/arch/sparc/isa/formats/priv.isa b/src/arch/sparc/isa/formats/priv.isa
index 1dc12e4..403a86e 100644
--- a/src/arch/sparc/isa/formats/priv.isa
+++ b/src/arch/sparc/isa/formats/priv.isa
@@ -40,7 +40,7 @@
def template PrivExecute {{
Fault
-%(class_name)s::execute(ExecContext *xc, Trace::InstRecord *traceData) const
+%(class_name)s::execute(ExecContext *xc, trace::InstRecord *traceData) const
{
%(op_decl)s;
%(op_rd)s;
diff --git a/src/arch/sparc/isa/formats/trap.isa b/src/arch/sparc/isa/formats/trap.isa
index 9d9a08b..5c0f21e 100644
--- a/src/arch/sparc/isa/formats/trap.isa
+++ b/src/arch/sparc/isa/formats/trap.isa
@@ -32,7 +32,7 @@
def template TrapExecute {{
Fault
%(class_name)s::execute(ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
Fault fault = NoFault;
%(op_decl)s;
@@ -45,7 +45,7 @@
def template FpUnimplExecute {{
Fault
%(class_name)s::execute(ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
Fault fault = NoFault;
%(op_decl)s;
diff --git a/src/arch/sparc/nativetrace.cc b/src/arch/sparc/nativetrace.cc
index ae2e169..3eee494 100644
--- a/src/arch/sparc/nativetrace.cc
+++ b/src/arch/sparc/nativetrace.cc
@@ -37,7 +37,7 @@
namespace gem5
{
-namespace Trace {
+namespace trace {
static const char *intRegNames[SparcISA::int_reg::NumArchRegs] = {
// Global registers
@@ -51,7 +51,7 @@
};
void
-Trace::SparcNativeTrace::check(NativeTraceRecord *record)
+SparcNativeTrace::check(NativeTraceRecord *record)
{
ThreadContext *tc = record->getThread();
@@ -89,5 +89,5 @@
checkReg("ccr", regVal, realRegVal);
}
-} // namespace Trace
+} // namespace trace
} // namespace gem5
diff --git a/src/arch/sparc/nativetrace.hh b/src/arch/sparc/nativetrace.hh
index 3a9d178..a45b742 100644
--- a/src/arch/sparc/nativetrace.hh
+++ b/src/arch/sparc/nativetrace.hh
@@ -37,7 +37,7 @@
class ThreadContext;
-namespace Trace {
+namespace trace {
class SparcNativeTrace : public NativeTrace
{
@@ -48,7 +48,7 @@
void check(NativeTraceRecord *record);
};
-} // namespace Trace
+} // namespace trace
} // namespace gem5
#endif // __CPU_NATIVETRACE_HH__
diff --git a/src/arch/x86/X86NativeTrace.py b/src/arch/x86/X86NativeTrace.py
index 5f06605..d0b94ec 100644
--- a/src/arch/x86/X86NativeTrace.py
+++ b/src/arch/x86/X86NativeTrace.py
@@ -32,5 +32,5 @@
class X86NativeTrace(NativeTrace):
type = "X86NativeTrace"
- cxx_class = "gem5::Trace::X86NativeTrace"
+ cxx_class = "gem5::trace::X86NativeTrace"
cxx_header = "arch/x86/nativetrace.hh"
diff --git a/src/arch/x86/insts/decode_fault.hh b/src/arch/x86/insts/decode_fault.hh
index ba70b3c..16b0f6b 100644
--- a/src/arch/x86/insts/decode_fault.hh
+++ b/src/arch/x86/insts/decode_fault.hh
@@ -58,7 +58,7 @@
{}
Fault
- execute(ExecContext *tc, Trace::InstRecord *traceData) const override
+ execute(ExecContext *tc, trace::InstRecord *traceData) const override
{
return fault;
}
diff --git a/src/arch/x86/insts/microdebug.hh b/src/arch/x86/insts/microdebug.hh
index 488ed14..1951705 100644
--- a/src/arch/x86/insts/microdebug.hh
+++ b/src/arch/x86/insts/microdebug.hh
@@ -49,7 +49,7 @@
{}
Fault
- execute(ExecContext *xc, Trace::InstRecord *traceData) const override
+ execute(ExecContext *xc, trace::InstRecord *traceData) const override
{
return fault;
}
diff --git a/src/arch/x86/insts/microspecop.hh b/src/arch/x86/insts/microspecop.hh
index 942bfd7..3e26dd3 100644
--- a/src/arch/x86/insts/microspecop.hh
+++ b/src/arch/x86/insts/microspecop.hh
@@ -49,7 +49,7 @@
{}
Fault
- execute(ExecContext *xc, Trace::InstRecord *) const override
+ execute(ExecContext *xc, trace::InstRecord *) const override
{
xc->tcBase()->suspend();
return NoFault;
diff --git a/src/arch/x86/isa/formats/basic.isa b/src/arch/x86/isa/formats/basic.isa
index 32e4087..8e2f8d6 100644
--- a/src/arch/x86/isa/formats/basic.isa
+++ b/src/arch/x86/isa/formats/basic.isa
@@ -49,7 +49,7 @@
public:
// Constructor.
%(class_name)s(ExtMachInst machInst);
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -66,7 +66,7 @@
// Basic instruction class execute method template.
def template BasicExecute {{
Fault %(class_name)s::execute(ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
Fault fault = NoFault;
diff --git a/src/arch/x86/isa/formats/cpuid.isa b/src/arch/x86/isa/formats/cpuid.isa
index 48557a2..aeffc10 100644
--- a/src/arch/x86/isa/formats/cpuid.isa
+++ b/src/arch/x86/isa/formats/cpuid.isa
@@ -66,7 +66,7 @@
def template CPUIDExecute {{
Fault %(class_name)s::execute(ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
// If the CPUID instruction used a valid function number, this will
// be set to true. Otherwise, the instruction does nothing.
diff --git a/src/arch/x86/isa/formats/monitor_mwait.isa b/src/arch/x86/isa/formats/monitor_mwait.isa
index de4343eab..d28a690 100644
--- a/src/arch/x86/isa/formats/monitor_mwait.isa
+++ b/src/arch/x86/isa/formats/monitor_mwait.isa
@@ -51,16 +51,16 @@
public:
// Constructor.
%(class_name)s(ExtMachInst machInst);
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
- Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
+ Fault initiateAcc(ExecContext *, trace::InstRecord *) const override;
Fault completeAcc(PacketPtr, ExecContext *,
- Trace::InstRecord *) const override;
+ trace::InstRecord *) const override;
};
}};
def template MwaitInitiateAcc {{
Fault %(class_name)s::initiateAcc(ExecContext * xc,
- Trace::InstRecord * traceData) const
+ trace::InstRecord * traceData) const
{
unsigned s = 0x8; //size
unsigned f = 0; //flags
@@ -71,7 +71,7 @@
def template MwaitCompleteAcc {{
Fault %(class_name)s::completeAcc(PacketPtr pkt, ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
MicroHalt hltObj(machInst, mnemonic, 0x0);
if(xc->mwait(pkt)) {
diff --git a/src/arch/x86/isa/formats/nop.isa b/src/arch/x86/isa/formats/nop.isa
index 24cbd1e..86d3af2 100644
--- a/src/arch/x86/isa/formats/nop.isa
+++ b/src/arch/x86/isa/formats/nop.isa
@@ -71,7 +71,7 @@
def template NopExecute {{
Fault %(class_name)s::execute(ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
return NoFault;
}
diff --git a/src/arch/x86/isa/formats/syscall.isa b/src/arch/x86/isa/formats/syscall.isa
index 59a3526..c36904f 100644
--- a/src/arch/x86/isa/formats/syscall.isa
+++ b/src/arch/x86/isa/formats/syscall.isa
@@ -71,7 +71,7 @@
def template SyscallExecute {{
Fault %(class_name)s::execute(ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
Fault fault = NoFault;
%(op_decl)s;
diff --git a/src/arch/x86/isa/formats/unimp.isa b/src/arch/x86/isa/formats/unimp.isa
index 9044a44..2950f55 100644
--- a/src/arch/x86/isa/formats/unimp.isa
+++ b/src/arch/x86/isa/formats/unimp.isa
@@ -60,7 +60,7 @@
flags[IsNonSpeculative] = true;
}
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
std::string
generateDisassembly(Addr pc,
@@ -92,7 +92,7 @@
flags[IsNonSpeculative] = true;
}
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
std::string
generateDisassembly(Addr pc,
@@ -119,7 +119,7 @@
output exec {{
Fault
FailUnimplemented::execute(ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
panic("attempt to execute unimplemented instruction '%s' %s",
mnemonic, machInst);
@@ -128,7 +128,7 @@
Fault
WarnUnimplemented::execute(ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
if (!warned) {
warn("instruction '%s' unimplemented\n", mnemonic);
diff --git a/src/arch/x86/isa/formats/unknown.isa b/src/arch/x86/isa/formats/unknown.isa
index 3e0dc55..eca297b 100644
--- a/src/arch/x86/isa/formats/unknown.isa
+++ b/src/arch/x86/isa/formats/unknown.isa
@@ -55,7 +55,7 @@
{
}
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
std::string generateDisassembly(
Addr pc, const loader::SymbolTable *symtab) const override;
@@ -74,7 +74,7 @@
output exec {{
Fault
- Unknown::execute(ExecContext *xc, Trace::InstRecord *traceData) const
+ Unknown::execute(ExecContext *xc, trace::InstRecord *traceData) const
{
return std::make_shared<InvalidOpcode>();
}
diff --git a/src/arch/x86/isa/macroop.isa b/src/arch/x86/isa/macroop.isa
index 6230760..691e8d0 100644
--- a/src/arch/x86/isa/macroop.isa
+++ b/src/arch/x86/isa/macroop.isa
@@ -43,7 +43,7 @@
// Execute method for macroops.
def template MacroExecPanic {{
Fault
- execute(ExecContext *, Trace::InstRecord *) const override
+ execute(ExecContext *, trace::InstRecord *) const override
{
panic("Tried to execute macroop directly!");
return NoFault;
@@ -61,7 +61,7 @@
{}
Fault
- execute(ExecContext *, Trace::InstRecord *) const override
+ execute(ExecContext *, trace::InstRecord *) const override
{
panic("Tried to execute macroop directly!");
}
diff --git a/src/arch/x86/isa/microops/debug.isa b/src/arch/x86/isa/microops/debug.isa
index 62c313f..44ccfbb 100644
--- a/src/arch/x86/isa/microops/debug.isa
+++ b/src/arch/x86/isa/microops/debug.isa
@@ -53,14 +53,14 @@
const char *inst_mnem, uint64_t set_flags,
GenericISA::M5DebugFault *_fault, uint8_t _cc);
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
def template MicroDebugFlagsExecute {{
Fault
%(class_name)s::execute(ExecContext *xc,
- Trace::InstRecord *trace_data) const
+ trace::InstRecord *trace_data) const
{
%(op_decl)s
%(op_rd)s
diff --git a/src/arch/x86/isa/microops/fpop.isa b/src/arch/x86/isa/microops/fpop.isa
index 6c6c5c1..5365c58 100644
--- a/src/arch/x86/isa/microops/fpop.isa
+++ b/src/arch/x86/isa/microops/fpop.isa
@@ -45,7 +45,7 @@
def template MicroFpOpExecute {{
Fault
%(class_name)s::execute(ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
Fault fault = NoFault;
@@ -82,7 +82,7 @@
uint64_t set_flags, uint8_t data_size, int8_t _spm,
Args... args);
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
diff --git a/src/arch/x86/isa/microops/ldstop.isa b/src/arch/x86/isa/microops/ldstop.isa
index 99a381a..5336f3a 100644
--- a/src/arch/x86/isa/microops/ldstop.isa
+++ b/src/arch/x86/isa/microops/ldstop.isa
@@ -47,7 +47,7 @@
def template MicroLeaExecute {{
Fault %(class_name)s::execute(ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
Fault fault = NoFault;
Addr EA;
@@ -84,7 +84,7 @@
%(constructor)s;
}
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -93,7 +93,7 @@
def template MicroLoadExecute {{
Fault
%(class_name)s::execute(ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
Fault fault = NoFault;
Addr EA;
@@ -122,7 +122,7 @@
def template MicroLoadInitiateAcc {{
Fault
%(class_name)s::initiateAcc(ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
Fault fault = NoFault;
Addr EA;
@@ -141,7 +141,7 @@
def template MicroLoadCompleteAcc {{
Fault
%(class_name)s::completeAcc(PacketPtr pkt, ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
Fault fault = NoFault;
@@ -165,7 +165,7 @@
def template MicroStoreExecute {{
Fault
%(class_name)s::execute(ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
Fault fault = NoFault;
@@ -192,7 +192,7 @@
def template MicroStoreInitiateAcc {{
Fault
%(class_name)s::initiateAcc(ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
Fault fault = NoFault;
@@ -215,7 +215,7 @@
def template MicroStoreCompleteAcc {{
Fault
%(class_name)s::completeAcc(PacketPtr pkt, ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
%(op_decl)s;
%(op_rd)s;
@@ -244,10 +244,10 @@
}
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
- Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
+ Fault initiateAcc(ExecContext *, trace::InstRecord *) const override;
Fault completeAcc(PacketPtr, ExecContext *,
- Trace::InstRecord *) const override;
+ trace::InstRecord *) const override;
};
}};
@@ -268,10 +268,10 @@
uint8_t data_size, uint8_t address_size,
Request::FlagsType mem_flags);
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
- Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
+ Fault initiateAcc(ExecContext *, trace::InstRecord *) const override;
Fault completeAcc(PacketPtr, ExecContext *,
- Trace::InstRecord *) const override;
+ trace::InstRecord *) const override;
};
}};
diff --git a/src/arch/x86/isa/microops/limmop.isa b/src/arch/x86/isa/microops/limmop.isa
index c1312e6..003407c 100644
--- a/src/arch/x86/isa/microops/limmop.isa
+++ b/src/arch/x86/isa/microops/limmop.isa
@@ -42,7 +42,7 @@
def template MicroLimmOpExecute {{
Fault
%(class_name)s::execute(ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
%(op_decl)s;
%(op_rd)s;
@@ -70,7 +70,7 @@
%(constructor)s;
}
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
diff --git a/src/arch/x86/isa/microops/mediaop.isa b/src/arch/x86/isa/microops/mediaop.isa
index 7d765b2..5fcf1d3 100644
--- a/src/arch/x86/isa/microops/mediaop.isa
+++ b/src/arch/x86/isa/microops/mediaop.isa
@@ -29,7 +29,7 @@
def template MediaOpExecute {{
Fault
%(class_name)s::execute(ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
Fault fault = NoFault;
@@ -64,7 +64,7 @@
%(constructor)s;
}
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
diff --git a/src/arch/x86/isa/microops/regop.isa b/src/arch/x86/isa/microops/regop.isa
index 3576c81..c7e9f46 100644
--- a/src/arch/x86/isa/microops/regop.isa
+++ b/src/arch/x86/isa/microops/regop.isa
@@ -42,7 +42,7 @@
def template MicroRegOpExecute {{
Fault
%(class_name)s::execute(ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
Fault fault = NoFault;
@@ -86,7 +86,7 @@
%(cond_control_flag_init)s;
}
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
@@ -109,7 +109,7 @@
%(cond_control_flag_init)s;
}
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
std::unique_ptr<PCStateBase> branchTarget(
const PCStateBase &branchPC) const override;
diff --git a/src/arch/x86/isa/microops/seqop.isa b/src/arch/x86/isa/microops/seqop.isa
index 1c8ce63..b24ef9e 100644
--- a/src/arch/x86/isa/microops/seqop.isa
+++ b/src/arch/x86/isa/microops/seqop.isa
@@ -49,7 +49,7 @@
%(constructor)s;
}
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
std::unique_ptr<PCStateBase>
branchTarget(const PCStateBase &branch_pc) const override
@@ -84,14 +84,14 @@
%(constructor)s;
}
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
def template SeqOpExecute {{
Fault
%(class_name)s::execute(ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
%(op_decl)s;
%(op_rd)s;
diff --git a/src/arch/x86/isa/microops/specop.isa b/src/arch/x86/isa/microops/specop.isa
index 7757e2d..da2f340 100644
--- a/src/arch/x86/isa/microops/specop.isa
+++ b/src/arch/x86/isa/microops/specop.isa
@@ -50,14 +50,14 @@
%(class_name)s(ExtMachInst mach_inst, const char *inst_mnem,
uint64_t set_flags, Fault _fault, uint8_t _cc);
- Fault execute(ExecContext *, Trace::InstRecord *) const override;
+ Fault execute(ExecContext *, trace::InstRecord *) const override;
};
}};
def template MicroFaultExecute {{
Fault
%(class_name)s::execute(ExecContext *xc,
- Trace::InstRecord *traceData) const
+ trace::InstRecord *traceData) const
{
%(op_decl)s;
%(op_rd)s;
@@ -144,7 +144,7 @@
uint64_t set_flags);
Fault
- execute(ExecContext *, Trace::InstRecord *) const override
+ execute(ExecContext *, trace::InstRecord *) const override
{
return NoFault;
}
diff --git a/src/arch/x86/memhelpers.hh b/src/arch/x86/memhelpers.hh
index 9ba4af8..54cbadf 100644
--- a/src/arch/x86/memhelpers.hh
+++ b/src/arch/x86/memhelpers.hh
@@ -45,7 +45,7 @@
/// Initiate a read from memory in timing mode.
static Fault
-initiateMemRead(ExecContext *xc, Trace::InstRecord *traceData, Addr addr,
+initiateMemRead(ExecContext *xc, trace::InstRecord *traceData, Addr addr,
unsigned dataSize, Request::Flags flags)
{
const std::vector<bool> byte_enable(dataSize, true);
@@ -54,7 +54,7 @@
static void
getMem(PacketPtr pkt, uint64_t &mem, unsigned dataSize,
- Trace::InstRecord *traceData)
+ trace::InstRecord *traceData)
{
switch (dataSize) {
case 1:
@@ -88,7 +88,7 @@
template <size_t N>
static void
getMem(PacketPtr pkt, std::array<uint64_t, N> &mem, unsigned dataSize,
- Trace::InstRecord *traceData)
+ trace::InstRecord *traceData)
{
switch (dataSize) {
case 4:
@@ -106,7 +106,7 @@
static Fault
-readMemAtomic(ExecContext *xc, Trace::InstRecord *traceData, Addr addr,
+readMemAtomic(ExecContext *xc, trace::InstRecord *traceData, Addr addr,
uint64_t &mem, unsigned dataSize, Request::Flags flags)
{
memset(&mem, 0, sizeof(mem));
@@ -145,7 +145,7 @@
template <size_t N>
static Fault
-readMemAtomic(ExecContext *xc, Trace::InstRecord *traceData, Addr addr,
+readMemAtomic(ExecContext *xc, trace::InstRecord *traceData, Addr addr,
std::array<uint64_t, N> &mem, unsigned dataSize,
unsigned flags)
{
@@ -183,7 +183,7 @@
}
static Fault
-writeMemTiming(ExecContext *xc, Trace::InstRecord *traceData, uint64_t mem,
+writeMemTiming(ExecContext *xc, trace::InstRecord *traceData, uint64_t mem,
unsigned dataSize, Addr addr, Request::Flags flags,
uint64_t *res)
{
@@ -197,7 +197,7 @@
template <size_t N>
static Fault
-writeMemTiming(ExecContext *xc, Trace::InstRecord *traceData,
+writeMemTiming(ExecContext *xc, trace::InstRecord *traceData,
std::array<uint64_t, N> &mem, unsigned dataSize,
Addr addr, unsigned flags, uint64_t *res)
{
@@ -215,7 +215,7 @@
}
static Fault
-writeMemAtomic(ExecContext *xc, Trace::InstRecord *traceData, uint64_t mem,
+writeMemAtomic(ExecContext *xc, trace::InstRecord *traceData, uint64_t mem,
unsigned dataSize, Addr addr, Request::Flags flags,
uint64_t *res)
{
@@ -232,7 +232,7 @@
template <size_t N>
static Fault
-writeMemAtomic(ExecContext *xc, Trace::InstRecord *traceData,
+writeMemAtomic(ExecContext *xc, trace::InstRecord *traceData,
std::array<uint64_t, N> &mem, unsigned dataSize,
Addr addr, unsigned flags, uint64_t *res)
{
diff --git a/src/arch/x86/nativetrace.cc b/src/arch/x86/nativetrace.cc
index 864825c..c999ffa 100644
--- a/src/arch/x86/nativetrace.cc
+++ b/src/arch/x86/nativetrace.cc
@@ -39,7 +39,7 @@
namespace gem5
{
-namespace Trace {
+namespace trace {
void
X86NativeTrace::ThreadState::update(NativeTrace *parent)
@@ -188,5 +188,5 @@
checkXMM(15, mState.xmm, nState.xmm);
}
-} // namespace Trace
+} // namespace trace
} // namespace gem5
diff --git a/src/arch/x86/nativetrace.hh b/src/arch/x86/nativetrace.hh
index 295be72..a4e17bc 100644
--- a/src/arch/x86/nativetrace.hh
+++ b/src/arch/x86/nativetrace.hh
@@ -37,7 +37,7 @@
class ThreadContext;
-namespace Trace {
+namespace trace {
class X86NativeTrace : public NativeTrace
{
@@ -87,7 +87,7 @@
void check(NativeTraceRecord *record);
};
-} // namespace Trace
+} // namespace trace
} // namespace gem5
#endif // __ARCH_X86_NATIVETRACE_HH__
diff --git a/src/base/trace.cc b/src/base/trace.cc
index b7a3a44..52faa8d 100644
--- a/src/base/trace.cc
+++ b/src/base/trace.cc
@@ -56,7 +56,7 @@
namespace gem5
{
-namespace Trace
+namespace trace
{
// This variable holds the output logger for debug information. Other
@@ -170,5 +170,5 @@
}
}
-} // namespace Trace
+} // namespace trace
} // namespace gem5
diff --git a/src/base/trace.hh b/src/base/trace.hh
index 05ad70e..a7f52eb 100644
--- a/src/base/trace.hh
+++ b/src/base/trace.hh
@@ -51,7 +51,7 @@
namespace gem5
{
-namespace Trace {
+namespace trace {
/** Debug logging base class. Handles formatting and outputting
* time/name/message messages */
@@ -138,7 +138,7 @@
void enable();
void disable();
-} // namespace Trace
+} // namespace trace
// This silly little class allows us to wrap a string in a functor
// object so that we can give a name() that DPRINTF will like
@@ -179,48 +179,48 @@
#define DDUMP(x, data, count) do { \
if (GEM5_UNLIKELY(TRACING_ON && ::gem5::debug::x)) \
- ::gem5::Trace::getDebugLogger()->dump( \
+ ::gem5::trace::getDebugLogger()->dump( \
::gem5::curTick(), name(), data, count, #x); \
} while (0)
#define DPRINTF(x, ...) do { \
if (GEM5_UNLIKELY(TRACING_ON && ::gem5::debug::x)) { \
- ::gem5::Trace::getDebugLogger()->dprintf_flag( \
+ ::gem5::trace::getDebugLogger()->dprintf_flag( \
::gem5::curTick(), name(), #x, __VA_ARGS__); \
} \
} while (0)
#define DPRINTFS(x, s, ...) do { \
if (GEM5_UNLIKELY(TRACING_ON && ::gem5::debug::x)) { \
- ::gem5::Trace::getDebugLogger()->dprintf_flag( \
+ ::gem5::trace::getDebugLogger()->dprintf_flag( \
::gem5::curTick(), (s)->name(), #x, __VA_ARGS__); \
} \
} while (0)
#define DPRINTFR(x, ...) do { \
if (GEM5_UNLIKELY(TRACING_ON && ::gem5::debug::x)) { \
- ::gem5::Trace::getDebugLogger()->dprintf_flag( \
+ ::gem5::trace::getDebugLogger()->dprintf_flag( \
(::gem5::Tick)-1, std::string(), #x, __VA_ARGS__); \
} \
} while (0)
#define DPRINTFV(x, ...) do { \
if (GEM5_UNLIKELY(TRACING_ON && (x))) { \
- ::gem5::Trace::getDebugLogger()->dprintf_flag( \
+ ::gem5::trace::getDebugLogger()->dprintf_flag( \
::gem5::curTick(), name(), x.name(), __VA_ARGS__); \
} \
} while (0)
#define DPRINTFN(...) do { \
if (TRACING_ON) { \
- ::gem5::Trace::getDebugLogger()->dprintf( \
+ ::gem5::trace::getDebugLogger()->dprintf( \
::gem5::curTick(), name(), __VA_ARGS__); \
} \
} while (0)
#define DPRINTFNR(...) do { \
if (TRACING_ON) { \
- ::gem5::Trace::getDebugLogger()->dprintf( \
+ ::gem5::trace::getDebugLogger()->dprintf( \
(::gem5::Tick)-1, "", __VA_ARGS__); \
} \
} while (0)
@@ -229,7 +229,7 @@
GEM5_DEPRECATED_MACRO_STMT(DPRINTF_UNCONDITIONAL, \
do { \
if (TRACING_ON) { \
- ::gem5::Trace::getDebugLogger()->dprintf_flag( \
+ ::gem5::trace::getDebugLogger()->dprintf_flag( \
::gem5::curTick(), name(), #x, __VA_ARGS__); \
} \
} while (0), \
diff --git a/src/base/trace.test.cc b/src/base/trace.test.cc
index 526e8dd..c53dcd7 100644
--- a/src/base/trace.test.cc
+++ b/src/base/trace.test.cc
@@ -43,7 +43,7 @@
// that getDebugLogger() returns a cerr-based logger, and all tests after
// that test should assume that this logger is returned
std::stringstream ss;
-Trace::OstreamLogger main_logger(ss);
+trace::OstreamLogger main_logger(ss);
// Instantiate the mock class to have a valid curTick of 0
GTestTickHandler tickHandler;
@@ -70,7 +70,7 @@
/** @return The logger's ostream as a std::string. */
std::string
-getString(Trace::Logger *logger)
+getString(trace::Logger *logger)
{
return getString(logger->getOstream());
}
@@ -79,7 +79,7 @@
TEST(TraceTest, LogSimpleMessage)
{
std::stringstream ss;
- Trace::OstreamLogger logger(ss);
+ trace::OstreamLogger logger(ss);
logger.logMessage(Tick(100), "", "", "Test message");
ASSERT_EQ(getString(&logger), " 100: Test message");
@@ -89,7 +89,7 @@
TEST(TraceTest, LogMessageName)
{
std::stringstream ss;
- Trace::OstreamLogger logger(ss);
+ trace::OstreamLogger logger(ss);
logger.logMessage(Tick(100), "Foo", "", "Test message");
ASSERT_EQ(getString(&logger), " 100: Foo: Test message");
@@ -99,7 +99,7 @@
TEST(TraceTest, LogMessageMaxTick)
{
std::stringstream ss;
- Trace::OstreamLogger logger(ss);
+ trace::OstreamLogger logger(ss);
logger.logMessage(MaxTick, "Foo", "", "Test message");
ASSERT_EQ(getString(&logger), "Foo: Test message");
@@ -109,7 +109,7 @@
TEST(TraceTest, LogMessageFlagDisabled)
{
std::stringstream ss;
- Trace::OstreamLogger logger(ss);
+ trace::OstreamLogger logger(ss);
logger.logMessage(Tick(100), "Foo", "Bar", "Test message");
ASSERT_EQ(getString(&logger), " 100: Foo: Test message");
@@ -122,12 +122,12 @@
TEST(TraceTest, LogMessageTickDisabledAndEnableDisable)
{
std::stringstream ss;
- Trace::OstreamLogger logger(ss);
+ trace::OstreamLogger logger(ss);
logger.logMessage(Tick(100), "Foo", "", "Test message");
ASSERT_EQ(getString(&logger), " 100: Foo: Test message");
- Trace::enable();
+ trace::enable();
EXPECT_TRUE(debug::changeFlag("FmtTicksOff", true));
logger.logMessage(Tick(200), "Foo", "", "Test message");
@@ -138,7 +138,7 @@
#endif
debug::changeFlag("FmtTicksOff", false);
- Trace::disable();
+ trace::disable();
logger.logMessage(Tick(300), "Foo", "", "Test message");
ASSERT_EQ(getString(&logger), " 300: Foo: Test message");
@@ -151,8 +151,8 @@
TEST(TraceTest, LogMessageFlagEnabled)
{
std::stringstream ss;
- Trace::OstreamLogger logger(ss);
- Trace::enable();
+ trace::OstreamLogger logger(ss);
+ trace::enable();
EXPECT_TRUE(debug::changeFlag("FmtFlag", true));
logger.logMessage(Tick(100), "Foo", "Bar", "Test message");
@@ -163,14 +163,14 @@
#endif
debug::changeFlag("FmtFlag", false);
- Trace::disable();
+ trace::disable();
}
/** Test that log messages are not displayed for ignored objects (single). */
TEST(TraceTest, LogMessageIgnoreOne)
{
std::stringstream ss;
- Trace::OstreamLogger logger(ss);
+ trace::OstreamLogger logger(ss);
ObjectMatch ignore_foo("Foo");
ObjectMatch ignore_bar("Bar");
@@ -194,7 +194,7 @@
TEST(TraceTest, LogMessageIgnoreMultiple)
{
std::stringstream ss;
- Trace::OstreamLogger logger(ss);
+ trace::OstreamLogger logger(ss);
ObjectMatch ignore_foo("Foo");
ObjectMatch ignore_bar("Bar");
@@ -225,7 +225,7 @@
TEST(TraceTest, DumpIgnored)
{
std::stringstream ss;
- Trace::OstreamLogger logger(ss);
+ trace::OstreamLogger logger(ss);
ObjectMatch ignore_foo("Foo");
logger.setIgnore(ignore_foo);
@@ -244,9 +244,9 @@
TEST(TraceTest, DumpSimple)
{
std::stringstream ss;
- Trace::OstreamLogger logger(ss);
+ trace::OstreamLogger logger(ss);
- Trace::enable();
+ trace::enable();
EXPECT_TRUE(debug::changeFlag("FmtFlag", true));
std::string message = "Test message";
logger.dump(Tick(100), "Foo", message.c_str(), message.size(), "Bar");
@@ -272,7 +272,7 @@
" Test message\n");
#endif
debug::changeFlag("FmtFlag", false);
- Trace::disable();
+ trace::disable();
}
/**
@@ -282,7 +282,7 @@
TEST(TraceTest, DumpMultiLine)
{
std::stringstream ss;
- Trace::OstreamLogger logger(ss);
+ trace::OstreamLogger logger(ss);
std::string message =
"This is a very long line that will span over multiple lines";
@@ -304,7 +304,7 @@
*/
TEST(TraceTest, DISABLED_GetNullLogger)
{
- Trace::Logger *logger = Trace::getDebugLogger();
+ trace::Logger *logger = trace::getDebugLogger();
ASSERT_FALSE(logger == nullptr);
gtestLogOutput.str("");
@@ -318,27 +318,27 @@
// NOTE: From now on getDebugLogger will use main_logger to avoid
// having to check cerr. This assumes that tests are run in the order
// they appear from line 1 to the last line of this file.
- Trace::setDebugLogger(&main_logger);
+ trace::setDebugLogger(&main_logger);
// Set message with local variable, and retrieve the string with
// the debug-logger getter
main_logger.logMessage(Tick(100), "Foo", "", "Test message");
- auto logger_from_getter = Trace::getDebugLogger();
+ auto logger_from_getter = trace::getDebugLogger();
ASSERT_EQ(getString(logger_from_getter), " 100: Foo: Test message");
}
/** Test that output() gets the ostream of the current debug logger. */
TEST(TraceTest, Output)
{
- Trace::getDebugLogger()->logMessage(Tick(100), "Foo", "", "Test message");
- ASSERT_EQ(getString(Trace::output()), " 100: Foo: Test message");
+ trace::getDebugLogger()->logMessage(Tick(100), "Foo", "", "Test message");
+ ASSERT_EQ(getString(trace::output()), " 100: Foo: Test message");
}
/** Test dprintf_flag with ignored name. */
TEST(TraceTest, DprintfFlagIgnore)
{
std::stringstream ss;
- Trace::OstreamLogger logger(ss);
+ trace::OstreamLogger logger(ss);
ObjectMatch ignore_foo("Foo");
logger.setIgnore(ignore_foo);
@@ -350,7 +350,7 @@
TEST(TraceTest, DprintfFlagZeroArgs)
{
std::stringstream ss;
- Trace::OstreamLogger logger(ss);
+ trace::OstreamLogger logger(ss);
logger.dprintf_flag(Tick(100), "Foo", "", "Test message");
ASSERT_EQ(getString(&logger), " 100: Foo: Test message");
@@ -360,7 +360,7 @@
TEST(TraceTest, DprintfFlagOneArg)
{
std::stringstream ss;
- Trace::OstreamLogger logger(ss);
+ trace::OstreamLogger logger(ss);
logger.dprintf_flag(Tick(100), "Foo", "", "Test %s", "message");
ASSERT_EQ(getString(&logger), " 100: Foo: Test message");
@@ -370,7 +370,7 @@
TEST(TraceTest, DprintfFlagMultipleArgs)
{
std::stringstream ss;
- Trace::OstreamLogger logger(ss);
+ trace::OstreamLogger logger(ss);
logger.dprintf_flag(Tick(100), "Foo", "", "Test %s %c %d %x",
"message", 'A', 217, 0x30);
@@ -381,9 +381,9 @@
TEST(TraceTest, DprintfFlagEnabled)
{
std::stringstream ss;
- Trace::OstreamLogger logger(ss);
+ trace::OstreamLogger logger(ss);
- Trace::enable();
+ trace::enable();
EXPECT_TRUE(debug::changeFlag("FmtFlag", true));
logger.dprintf_flag(Tick(100), "Foo", "Bar", "Test %s", "message");
#if TRACING_ON
@@ -392,14 +392,14 @@
ASSERT_EQ(getString(&logger), " 100: Foo: Test message");
#endif
debug::changeFlag("FmtFlag", false);
- Trace::disable();
+ trace::disable();
}
/** Test dprintf with ignored name. */
TEST(TraceTest, DprintfIgnore)
{
std::stringstream ss;
- Trace::OstreamLogger logger(ss);
+ trace::OstreamLogger logger(ss);
ObjectMatch ignore_foo("Foo");
logger.setIgnore(ignore_foo);
@@ -411,22 +411,22 @@
TEST(TraceTest, DprintfEnabled)
{
std::stringstream ss;
- Trace::OstreamLogger logger(ss);
+ trace::OstreamLogger logger(ss);
- Trace::enable();
+ trace::enable();
EXPECT_TRUE(debug::changeFlag("FmtFlag", true));
logger.dprintf(Tick(100), "Foo", "Test %s", "message");
ASSERT_EQ(getString(&logger), " 100: Foo: Test message");
debug::changeFlag("FmtFlag", false);
- Trace::disable();
+ trace::disable();
}
/** Test that dprintf is just a flagless wrapper for dprintf_flag. */
TEST(TraceTest, DprintfWrapper)
{
std::stringstream ss, ss_flag;
- Trace::OstreamLogger logger(ss);
- Trace::OstreamLogger logger_flag(ss_flag);
+ trace::OstreamLogger logger(ss);
+ trace::OstreamLogger logger_flag(ss_flag);
logger.dprintf(Tick(100), "Foo", "Test %s %c %d %x",
"message", 'A', 217, 0x30);
@@ -442,23 +442,23 @@
std::string message = "Test message";
// Flag enabled
- Trace::enable();
+ trace::enable();
EXPECT_TRUE(debug::changeFlag("TraceTestDebugFlag", true));
EXPECT_TRUE(debug::changeFlag("FmtFlag", true));
DDUMP(TraceTestDebugFlag, message.c_str(), message.size());
#if TRACING_ON
- ASSERT_EQ(getString(Trace::output()),
+ ASSERT_EQ(getString(trace::output()),
" 0: TraceTestDebugFlag: Foo: 00000000 "
"54 65 73 74 20 6d 65 73 73 61 67 65 Test message\n");
#else
- ASSERT_EQ(getString(Trace::output()), "");
+ ASSERT_EQ(getString(trace::output()), "");
#endif
// Flag disabled
- Trace::disable();
+ trace::disable();
EXPECT_TRUE(debug::changeFlag("TraceTestDebugFlag", false));
DDUMP(TraceTestDebugFlag, message.c_str(), message.size());
- ASSERT_EQ(getString(Trace::output()), "");
+ ASSERT_EQ(getString(trace::output()), "");
}
/** Test DPRINTF with tracing on. */
@@ -467,22 +467,22 @@
StringWrap name("Foo");
// Flag enabled
- Trace::enable();
+ trace::enable();
EXPECT_TRUE(debug::changeFlag("TraceTestDebugFlag", true));
EXPECT_TRUE(debug::changeFlag("FmtFlag", true));
DPRINTF(TraceTestDebugFlag, "Test message");
#if TRACING_ON
- ASSERT_EQ(getString(Trace::output()),
+ ASSERT_EQ(getString(trace::output()),
" 0: TraceTestDebugFlag: Foo: Test message");
#else
- ASSERT_EQ(getString(Trace::output()), "");
+ ASSERT_EQ(getString(trace::output()), "");
#endif
// Flag disabled
- Trace::disable();
+ trace::disable();
EXPECT_TRUE(debug::changeFlag("TraceTestDebugFlag", false));
DPRINTF(TraceTestDebugFlag, "Test message");
- ASSERT_EQ(getString(Trace::output()), "");
+ ASSERT_EQ(getString(trace::output()), "");
}
/** Test DPRINTFS with tracing on. */
@@ -494,21 +494,21 @@
#endif
// Flag enabled
- Trace::enable();
+ trace::enable();
EXPECT_TRUE(debug::changeFlag("TraceTestDebugFlag", true));
EXPECT_TRUE(debug::changeFlag("FmtFlag", true));
#if TRACING_ON
DPRINTFS(TraceTestDebugFlag, named_ptr, "Test message");
- ASSERT_EQ(getString(Trace::output()),
+ ASSERT_EQ(getString(trace::output()),
" 0: TraceTestDebugFlag: Foo: Test message");
#endif
// Flag disabled
- Trace::disable();
+ trace::disable();
EXPECT_TRUE(debug::changeFlag("TraceTestDebugFlag", false));
#if TRACING_ON
DPRINTFS(TraceTestDebugFlag, named_ptr, "Test message");
- ASSERT_EQ(getString(Trace::output()), "");
+ ASSERT_EQ(getString(trace::output()), "");
#endif
}
@@ -516,21 +516,21 @@
TEST(TraceTest, MacroDPRINTFR)
{
// Flag enabled
- Trace::enable();
+ trace::enable();
EXPECT_TRUE(debug::changeFlag("TraceTestDebugFlag", true));
EXPECT_TRUE(debug::changeFlag("FmtFlag", true));
DPRINTFR(TraceTestDebugFlag, "Test message");
#if TRACING_ON
- ASSERT_EQ(getString(Trace::output()), "TraceTestDebugFlag: Test message");
+ ASSERT_EQ(getString(trace::output()), "TraceTestDebugFlag: Test message");
#else
- ASSERT_EQ(getString(Trace::output()), "");
+ ASSERT_EQ(getString(trace::output()), "");
#endif
// Flag disabled
- Trace::disable();
+ trace::disable();
EXPECT_TRUE(debug::changeFlag("TraceTestDebugFlag", false));
DPRINTFR(TraceTestDebugFlag, "Test message");
- ASSERT_EQ(getString(Trace::output()), "");
+ ASSERT_EQ(getString(trace::output()), "");
}
/** Test DPRINTFN with tracing on. */
@@ -539,9 +539,9 @@
StringWrap name("Foo");
DPRINTFN("Test message");
#if TRACING_ON
- ASSERT_EQ(getString(Trace::output()), " 0: Foo: Test message");
+ ASSERT_EQ(getString(trace::output()), " 0: Foo: Test message");
#else
- ASSERT_EQ(getString(Trace::output()), "");
+ ASSERT_EQ(getString(trace::output()), "");
#endif
}
@@ -550,9 +550,9 @@
{
DPRINTFNR("Test message");
#if TRACING_ON
- ASSERT_EQ(getString(Trace::output()), "Test message");
+ ASSERT_EQ(getString(trace::output()), "Test message");
#else
- ASSERT_EQ(getString(Trace::output()), "");
+ ASSERT_EQ(getString(trace::output()), "");
#endif
}
@@ -562,25 +562,25 @@
StringWrap name("Foo");
// Flag enabled
- Trace::enable();
+ trace::enable();
EXPECT_TRUE(debug::changeFlag("TraceTestDebugFlag", true));
EXPECT_TRUE(debug::changeFlag("FmtFlag", true));
DPRINTF_UNCONDITIONAL(TraceTestDebugFlag, "Test message");
#if TRACING_ON
- ASSERT_EQ(getString(Trace::output()),
+ ASSERT_EQ(getString(trace::output()),
" 0: TraceTestDebugFlag: Foo: Test message");
#else
- ASSERT_EQ(getString(Trace::output()), "");
+ ASSERT_EQ(getString(trace::output()), "");
#endif
// Flag disabled
- Trace::disable();
+ trace::disable();
EXPECT_TRUE(debug::changeFlag("TraceTestDebugFlag", false));
DPRINTF_UNCONDITIONAL(TraceTestDebugFlag, "Test message");
#if TRACING_ON
- ASSERT_EQ(getString(Trace::output()), " 0: Foo: Test message");
+ ASSERT_EQ(getString(trace::output()), " 0: Foo: Test message");
#else
- ASSERT_EQ(getString(Trace::output()), "");
+ ASSERT_EQ(getString(trace::output()), "");
#endif
}
@@ -591,20 +591,20 @@
TEST(TraceTest, GlobalName)
{
// Flag enabled
- Trace::enable();
+ trace::enable();
EXPECT_TRUE(debug::changeFlag("TraceTestDebugFlag", true));
EXPECT_TRUE(debug::changeFlag("FmtFlag", true));
DPRINTF(TraceTestDebugFlag, "Test message");
#if TRACING_ON
- ASSERT_EQ(getString(Trace::output()),
+ ASSERT_EQ(getString(trace::output()),
" 0: TraceTestDebugFlag: global: Test message");
#else
- ASSERT_EQ(getString(Trace::output()), "");
+ ASSERT_EQ(getString(trace::output()), "");
#endif
// Flag disabled
- Trace::disable();
+ trace::disable();
EXPECT_TRUE(debug::changeFlag("TraceTestDebugFlag", false));
DPRINTF(TraceTestDebugFlag, "Test message");
- ASSERT_EQ(getString(Trace::output()), "");
+ ASSERT_EQ(getString(trace::output()), "");
}
diff --git a/src/cpu/CPUTracers.py b/src/cpu/CPUTracers.py
index eb0ce6a..f491a0e 100644
--- a/src/cpu/CPUTracers.py
+++ b/src/cpu/CPUTracers.py
@@ -31,18 +31,18 @@
class ExeTracer(InstTracer):
type = "ExeTracer"
- cxx_class = "gem5::Trace::ExeTracer"
+ cxx_class = "gem5::trace::ExeTracer"
cxx_header = "cpu/exetrace.hh"
class IntelTrace(InstTracer):
type = "IntelTrace"
- cxx_class = "gem5::Trace::IntelTrace"
+ cxx_class = "gem5::trace::IntelTrace"
cxx_header = "cpu/inteltrace.hh"
class NativeTrace(ExeTracer):
abstract = True
type = "NativeTrace"
- cxx_class = "gem5::Trace::NativeTrace"
+ cxx_class = "gem5::trace::NativeTrace"
cxx_header = "cpu/nativetrace.hh"
diff --git a/src/cpu/InstPBTrace.py b/src/cpu/InstPBTrace.py
index 0bfee94..167443d 100644
--- a/src/cpu/InstPBTrace.py
+++ b/src/cpu/InstPBTrace.py
@@ -32,6 +32,6 @@
class InstPBTrace(InstTracer):
type = "InstPBTrace"
- cxx_class = "gem5::Trace::InstPBTrace"
+ cxx_class = "gem5::trace::InstPBTrace"
cxx_header = "cpu/inst_pb_trace.hh"
file_name = Param.String("Instruction trace output file")
diff --git a/src/cpu/base.hh b/src/cpu/base.hh
index 7856e17..0d56fba 100644
--- a/src/cpu/base.hh
+++ b/src/cpu/base.hh
@@ -255,7 +255,7 @@
protected:
std::vector<ThreadContext *> threadContexts;
- Trace::InstTracer * tracer;
+ trace::InstTracer * tracer;
public:
@@ -265,7 +265,7 @@
static const uint32_t invldPid = std::numeric_limits<uint32_t>::max();
/// Provide access to the tracer pointer
- Trace::InstTracer * getTracer() { return tracer; }
+ trace::InstTracer * getTracer() { return tracer; }
/// Notify the CPU that the indicated context is now active.
virtual void activateContext(ThreadID thread_num);
diff --git a/src/cpu/checker/cpu_impl.hh b/src/cpu/checker/cpu_impl.hh
index 4c728db..cb6e57c 100644
--- a/src/cpu/checker/cpu_impl.hh
+++ b/src/cpu/checker/cpu_impl.hh
@@ -346,7 +346,7 @@
if (fault == NoFault) {
// Execute Checker instruction and trace
if (!unverifiedInst->isUnverifiable()) {
- Trace::InstRecord *traceData = tracer->getInstRecord(curTick(),
+ trace::InstRecord *traceData = tracer->getInstRecord(curTick(),
tc,
curStaticInst,
pcState(),
diff --git a/src/cpu/exetrace.cc b/src/cpu/exetrace.cc
index bb5add8..22d0d4b 100644
--- a/src/cpu/exetrace.cc
+++ b/src/cpu/exetrace.cc
@@ -54,10 +54,10 @@
namespace gem5
{
-namespace Trace {
+namespace trace {
void
-Trace::ExeTracerRecord::traceInst(const StaticInstPtr &inst, bool ran)
+ExeTracerRecord::traceInst(const StaticInstPtr &inst, bool ran)
{
std::stringstream outs;
@@ -142,13 +142,13 @@
//
outs << std::endl;
- Trace::getDebugLogger()->dprintf_flag(
+ trace::getDebugLogger()->dprintf_flag(
when, thread->getCpuPtr()->name(), "ExecEnable", "%s",
outs.str().c_str());
}
void
-Trace::ExeTracerRecord::dump()
+ExeTracerRecord::dump()
{
/*
* The behavior this check tries to achieve is that if ExecMacro is on,
@@ -170,5 +170,5 @@
}
}
-} // namespace Trace
+} // namespace trace
} // namespace gem5
diff --git a/src/cpu/exetrace.hh b/src/cpu/exetrace.hh
index 7210241..143cfa0 100644
--- a/src/cpu/exetrace.hh
+++ b/src/cpu/exetrace.hh
@@ -42,7 +42,7 @@
class ThreadContext;
-namespace Trace {
+namespace trace {
class ExeTracerRecord : public InstRecord
{
@@ -79,7 +79,7 @@
}
};
-} // namespace Trace
+} // namespace trace
} // namespace gem5
#endif // __CPU_EXETRACE_HH__
diff --git a/src/cpu/inst_pb_trace.cc b/src/cpu/inst_pb_trace.cc
index ccbb372..4a289f0 100644
--- a/src/cpu/inst_pb_trace.cc
+++ b/src/cpu/inst_pb_trace.cc
@@ -50,7 +50,7 @@
namespace gem5
{
-namespace Trace {
+namespace trace {
ProtoOutputStream *InstPBTrace::traceStream;
@@ -177,5 +177,5 @@
}
-} // namespace Trace
+} // namespace trace
} // namespace gem5
diff --git a/src/cpu/inst_pb_trace.hh b/src/cpu/inst_pb_trace.hh
index ee0ed64..52924f8 100644
--- a/src/cpu/inst_pb_trace.hh
+++ b/src/cpu/inst_pb_trace.hh
@@ -55,7 +55,7 @@
class ThreadContext;
-namespace Trace {
+namespace trace {
/**
* This in an instruction tracer that records the flow of instructions through
@@ -136,7 +136,7 @@
friend class InstPBTraceRecord;
};
-} // namespace Trace
+} // namespace trace
} // namespace gem5
#endif // __CPU_INST_PB_TRACE_HH__
diff --git a/src/cpu/inteltrace.cc b/src/cpu/inteltrace.cc
index 0c3c6c2..3aea5c6 100644
--- a/src/cpu/inteltrace.cc
+++ b/src/cpu/inteltrace.cc
@@ -36,12 +36,12 @@
namespace gem5
{
-namespace Trace {
+namespace trace {
void
-Trace::IntelTraceRecord::dump()
+IntelTraceRecord::dump()
{
- std::ostream &outs = Trace::output();
+ std::ostream &outs = trace::output();
ccprintf(outs, "%7d ) ", when);
outs << "0x" << std::hex << pc->instAddr() << ":\t";
if (staticInst->isLoad()) {
@@ -52,5 +52,5 @@
outs << std::endl;
}
-} // namespace Trace
+} // namespace trace
} // namespace gem5
diff --git a/src/cpu/inteltrace.hh b/src/cpu/inteltrace.hh
index 4d57026..3ccfe35 100644
--- a/src/cpu/inteltrace.hh
+++ b/src/cpu/inteltrace.hh
@@ -40,7 +40,7 @@
namespace gem5
{
-namespace Trace {
+namespace trace {
class IntelTraceRecord : public InstRecord
{
@@ -75,7 +75,7 @@
}
};
-} // namespace Trace
+} // namespace trace
} // namespace gem5
#endif // __CPU_INTELTRACE_HH__
diff --git a/src/cpu/minor/dyn_inst.hh b/src/cpu/minor/dyn_inst.hh
index 0342434..d9a85f9 100644
--- a/src/cpu/minor/dyn_inst.hh
+++ b/src/cpu/minor/dyn_inst.hh
@@ -173,7 +173,7 @@
InstId id;
/** Trace information for this instruction's execution */
- Trace::InstRecord *traceData = nullptr;
+ trace::InstRecord *traceData = nullptr;
/** The fetch address of this instruction */
std::unique_ptr<PCStateBase> pc;
diff --git a/src/cpu/nativetrace.cc b/src/cpu/nativetrace.cc
index 0686bca..5b7d0b9 100644
--- a/src/cpu/nativetrace.cc
+++ b/src/cpu/nativetrace.cc
@@ -36,7 +36,7 @@
namespace gem5
{
-namespace Trace {
+namespace trace {
NativeTrace::NativeTrace(const Params &p)
: ExeTracer(p)
@@ -55,7 +55,7 @@
}
void
-Trace::NativeTraceRecord::dump()
+NativeTraceRecord::dump()
{
//Don't print what happens for each micro-op, just print out
//once at the last op, and for regular instructions.
@@ -63,5 +63,5 @@
parent->check(this);
}
-} // namespace Trace
+} // namespace trace
} // namespace gem5
diff --git a/src/cpu/nativetrace.hh b/src/cpu/nativetrace.hh
index e2756bc..a00e97a 100644
--- a/src/cpu/nativetrace.hh
+++ b/src/cpu/nativetrace.hh
@@ -44,7 +44,7 @@
class ThreadContext;
-namespace Trace {
+namespace trace {
class NativeTrace;
@@ -117,7 +117,7 @@
check(NativeTraceRecord *record) = 0;
};
-} // namespace Trace
+} // namespace trace
} // namespace gem5
#endif // __CPU_NATIVETRACE_HH__
diff --git a/src/cpu/nop_static_inst.cc b/src/cpu/nop_static_inst.cc
index 4b73aa0..929f297 100644
--- a/src/cpu/nop_static_inst.cc
+++ b/src/cpu/nop_static_inst.cc
@@ -43,7 +43,7 @@
NopStaticInst() : StaticInst("gem5 nop", No_OpClass) {}
Fault
- execute(ExecContext *xc, Trace::InstRecord *traceData) const override
+ execute(ExecContext *xc, trace::InstRecord *traceData) const override
{
return NoFault;
}
diff --git a/src/cpu/o3/dyn_inst.hh b/src/cpu/o3/dyn_inst.hh
index 1a55ef7..ab165bb 100644
--- a/src/cpu/o3/dyn_inst.hh
+++ b/src/cpu/o3/dyn_inst.hh
@@ -137,7 +137,7 @@
Fault fault = NoFault;
/** InstRecord that tracks this instructions. */
- Trace::InstRecord *traceData = nullptr;
+ trace::InstRecord *traceData = nullptr;
protected:
enum Status
diff --git a/src/cpu/simple/base.hh b/src/cpu/simple/base.hh
index 3fdd019..df5290c 100644
--- a/src/cpu/simple/base.hh
+++ b/src/cpu/simple/base.hh
@@ -68,7 +68,7 @@
class Processor;
class ThreadContext;
-namespace Trace
+namespace trace
{
class InstRecord;
}
@@ -94,7 +94,7 @@
virtual ~BaseSimpleCPU();
void wakeup(ThreadID tid) override;
public:
- Trace::InstRecord *traceData;
+ trace::InstRecord *traceData;
CheckerCPU *checker;
std::vector<SimpleExecContext*> threadInfo;
diff --git a/src/cpu/static_inst.hh b/src/cpu/static_inst.hh
index af5975e..21ce2aa 100644
--- a/src/cpu/static_inst.hh
+++ b/src/cpu/static_inst.hh
@@ -72,10 +72,10 @@
class SymbolTable;
} // namespace loader
-namespace Trace
+namespace trace
{
class InstRecord;
-} // namespace Trace
+} // namespace trace
/**
* Base, ISA-independent static instruction class.
@@ -283,17 +283,17 @@
virtual ~StaticInst() {};
virtual Fault execute(ExecContext *xc,
- Trace::InstRecord *traceData) const = 0;
+ trace::InstRecord *traceData) const = 0;
virtual Fault
- initiateAcc(ExecContext *xc, Trace::InstRecord *traceData) const
+ initiateAcc(ExecContext *xc, trace::InstRecord *traceData) const
{
panic("initiateAcc not defined!");
}
virtual Fault
completeAcc(Packet *pkt, ExecContext *xc,
- Trace::InstRecord *trace_data) const
+ trace::InstRecord *trace_data) const
{
panic("completeAcc not defined!");
}
diff --git a/src/python/pybind11/debug.cc b/src/python/pybind11/debug.cc
index 3fc3d09..9ac8724 100644
--- a/src/python/pybind11/debug.cc
+++ b/src/python/pybind11/debug.cc
@@ -64,7 +64,7 @@
if (!file_stream)
file_stream = simout.create(filename);
- Trace::setDebugLogger(new Trace::OstreamLogger(*file_stream->stream()));
+ trace::setDebugLogger(new trace::OstreamLogger(*file_stream->stream()));
}
static void
@@ -72,7 +72,7 @@
{
ObjectMatch ignore(expr);
- Trace::getDebugLogger()->addIgnore(ignore);
+ trace::getDebugLogger()->addIgnore(ignore);
}
void
@@ -123,8 +123,8 @@
m_trace
.def("output", &output)
.def("ignore", &ignore)
- .def("enable", &Trace::enable)
- .def("disable", &Trace::disable)
+ .def("enable", &trace::enable)
+ .def("disable", &trace::disable)
;
}
diff --git a/src/sim/InstTracer.py b/src/sim/InstTracer.py
index 3b85965..34c97dd 100644
--- a/src/sim/InstTracer.py
+++ b/src/sim/InstTracer.py
@@ -31,5 +31,5 @@
class InstTracer(SimObject):
type = "InstTracer"
cxx_header = "sim/insttracer.hh"
- cxx_class = "gem5::Trace::InstTracer"
+ cxx_class = "gem5::trace::InstTracer"
abstract = True
diff --git a/src/sim/insttracer.hh b/src/sim/insttracer.hh
index e296a1e..9c9bca7 100644
--- a/src/sim/insttracer.hh
+++ b/src/sim/insttracer.hh
@@ -55,7 +55,7 @@
class ThreadContext;
-namespace Trace {
+namespace trace {
class InstRecord
{
@@ -299,7 +299,7 @@
const StaticInstPtr macroStaticInst=nullptr) = 0;
};
-} // namespace Trace
+} // namespace trace
} // namespace gem5
#endif // __INSTRECORD_HH__
diff --git a/util/systemc/gem5_within_systemc/main.cc b/util/systemc/gem5_within_systemc/main.cc
index c7f9dd6..2d45350 100644
--- a/util/systemc/gem5_within_systemc/main.cc
+++ b/util/systemc/gem5_within_systemc/main.cc
@@ -157,7 +157,7 @@
usage(prog_name);
/* Pass DPRINTF messages to SystemC */
- Trace::setDebugLogger(&logger);
+ trace::setDebugLogger(&logger);
/* @todo need this as an option */
Gem5SystemC::setTickFrequency();
@@ -179,7 +179,7 @@
statistics::initSimStats();
statistics::registerHandlers(CxxConfig::statsReset, CxxConfig::statsDump);
- Trace::enable();
+ trace::enable();
setDebugFlag("Terminal");
checkpoint_restore = false;
diff --git a/util/systemc/gem5_within_systemc/sc_gem5_control.cc b/util/systemc/gem5_within_systemc/sc_gem5_control.cc
index 568c0eb..db2f00f 100644
--- a/util/systemc/gem5_within_systemc/sc_gem5_control.cc
+++ b/util/systemc/gem5_within_systemc/sc_gem5_control.cc
@@ -215,7 +215,7 @@
SC_THREAD(run);
/* Pass DPRINTF messages to SystemC */
- gem5::Trace::setDebugLogger(&logger);
+ gem5::trace::setDebugLogger(&logger);
/* @todo need this as an option */
Gem5SystemC::setTickFrequency();
@@ -238,7 +238,7 @@
gem5::statistics::registerHandlers(CxxConfig::statsReset,
CxxConfig::statsDump);
- gem5::Trace::enable();
+ gem5::trace::enable();
config_file = new gem5::CxxIniFile();
diff --git a/util/systemc/gem5_within_systemc/sc_logger.cc b/util/systemc/gem5_within_systemc/sc_logger.cc
index c833cc5..1b7553a 100644
--- a/util/systemc/gem5_within_systemc/sc_logger.cc
+++ b/util/systemc/gem5_within_systemc/sc_logger.cc
@@ -60,9 +60,9 @@
std::ostringstream line;
/** Logger to send complete lines to */
- gem5::Trace::Logger *logger;
+ gem5::trace::Logger *logger;
- CuttingStreambuf(gem5::Trace::Logger *logger_) : logger(logger_)
+ CuttingStreambuf(gem5::trace::Logger *logger_) : logger(logger_)
{ }
/** Accumulate to line up to \n and then emit */
diff --git a/util/systemc/gem5_within_systemc/sc_logger.hh b/util/systemc/gem5_within_systemc/sc_logger.hh
index cbcea31..01e700b 100644
--- a/util/systemc/gem5_within_systemc/sc_logger.hh
+++ b/util/systemc/gem5_within_systemc/sc_logger.hh
@@ -53,7 +53,7 @@
{
/** sc_report logging class */
-class Logger : public gem5::Trace::Logger
+class Logger : public gem5::trace::Logger
{
protected:
/** Stream to offer getOstream. This will cut messages up newlines and
diff --git a/util/tlm/src/sim_control.cc b/util/tlm/src/sim_control.cc
index c706fd9..a8a3da4 100644
--- a/util/tlm/src/sim_control.cc
+++ b/util/tlm/src/sim_control.cc
@@ -80,7 +80,7 @@
gem5::ExternalMaster::registerHandler("tlm_master",
new SCMasterPortHandler(*this));
- gem5::Trace::setDebugLogger(&logger);
+ gem5::trace::setDebugLogger(&logger);
Gem5SystemC::setTickFrequency();
assert(sc_core::sc_get_time_resolution()
@@ -93,7 +93,7 @@
gem5::statistics::registerHandlers(CxxConfig::statsReset,
CxxConfig::statsDump);
- gem5::Trace::enable();
+ gem5::trace::enable();
gem5::CxxConfigFileBase* conf = new gem5::CxxIniFile();
