util/tlm/src/master_transactor.hh

/*
 * Copyright (c) 2016, Dresden University of Technology (TU Dresden)
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are
 * met:
 *
 * 1. Redistributions of source code must retain the above copyright notice,
 *    this list of conditions and the following disclaimer.
 *
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimer in the
 *    documentation and/or other materials provided with the distribution.
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 * 3. Neither the name of the copyright holder nor the names of its
 *    contributors may be used to endorse or promote products derived from
 *    this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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 */

#ifndef __GEM5_MASTER_TRANSACTOR_HH__
#define __GEM5_MASTER_TRANSACTOR_HH__

#include <tlm_utils/simple_target_socket.h>

#include <systemc>
#include <tlm>

#include "sc_master_port.hh"
#include "sim_control_if.hh"

namespace Gem5SystemC
{

class Gem5MasterTransactor : public sc_core::sc_module
{
  public:
    // module interface
    tlm_utils::simple_target_socket<SCMasterPort> socket;
    sc_core::sc_port<Gem5SimControlInterface> sim_control;

  private:
    std::string portName;

  public:
    SC_HAS_PROCESS(Gem5MasterTransactor);

    Gem5MasterTransactor(sc_core::sc_module_name name,
                         const std::string& portName);

    void before_end_of_elaboration();
};

}

#endif