| # Copyright (c) 2022 The Regents of the University of California |
| # All rights reserved. |
| # |
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| # documentation and/or other materials provided with the distribution; |
| # neither the name of the copyright holders nor the names of its |
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| # this software without specific prior written permission. |
| # |
| # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
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| |
| |
| from m5.objects import Port, TrafficGen |
| |
| from .abstract_core import AbstractCore |
| from .abstract_generator_core import AbstractGeneratorCore |
| from ...utils.override import overrides |
| |
| |
| class TrafficGeneratorCore(AbstractGeneratorCore): |
| """The traffic generator core interface. |
| |
| This class defines the interface for a generator core that will create |
| a compound traffic specified by the parameters below. It uses |
| TrafficGen to create the traffic. |
| |
| :param config_file: path to the configuration file specifying the |
| pattern of traffic. |
| """ |
| |
| def __init__(self, config_file: str): |
| """ |
| Create a TrafficGen SimObject as the core of this component. |
| """ |
| super().__init__() |
| self.generator = TrafficGen(config_file=config_file) |
| |
| @overrides(AbstractCore) |
| def connect_dcache(self, port: Port) -> None: |
| self.generator.port = port |