src/mem/ruby/slicc_interface/RubyRequest.cc

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 * Copyright (c) 2011 Mark D. Hill and David A. Wood
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#include "mem/ruby/slicc_interface/RubyRequest.hh"

#include <iostream>

#include "mem/ruby/slicc_interface/RubySlicc_Util.hh"

namespace gem5
{

namespace ruby
{

void
RubyRequest::print(std::ostream& out) const
{
  out << "[RubyRequest: ";
  out << std::hex << "LineAddress = 0x" << m_LineAddress << std::dec << " ";
  out << std::hex << "PhysicalAddress = 0x" << m_PhysicalAddress;
  out << std::dec << " " << "Type = " << m_Type << " ";
  out << std::hex << "ProgramCounter = 0x" << m_ProgramCounter << std::dec;
  out << " " << "AccessMode = " << m_AccessMode << " ";
  out << "Size = " << m_Size << " ";
  out << "Prefetch = " << m_Prefetch << " ";
//  out << "Time = " << getTime() << " ";
  out << "]";
}

bool
RubyRequest::functionalRead(Packet *pkt)
{
    // This needs a little explanation. Initially I thought that this
    // message should be read. But the way the memtester works for now,
    // we should not be reading this message as memtester updates the
    // functional memory only after a write has actually taken place.
    return false;
}

bool
RubyRequest::functionalRead(Packet *pkt, WriteMask &mask)
{
    return false;
}

bool
RubyRequest::functionalWrite(Packet *pkt)
{
    // This needs a little explanation. I am not sure if this message
    // should be written. Essentially the question is how are writes
    // ordered. I am assuming that if a functional write is issued after
    // a timing write to the same address, then the functional write
    // has to overwrite the data for the timing request, even if the
    // timing request has still not been ordered globally.

    if (!pkt->hasData() || !m_pkt->hasData())
        return false;

    uint8_t *data =  m_pkt->getPtr<uint8_t>();

    if (pkt->isMaskedWrite() || m_pkt->isMaskedWrite()) {
        warn("Skiping functional write to/from a masked write packet"
            " (addr: %#x, other addr: %#x).\n", m_PhysicalAddress,
              pkt->getAddr());
        return false;
    }

    Addr wBase = pkt->getAddr();
    Addr wTail = wBase + pkt->getSize();
    Addr mBase = m_PhysicalAddress;
    Addr mTail = mBase + m_Size;

    const uint8_t * pktData = pkt->getConstPtr<uint8_t>();

    Addr cBase = std::max(wBase, mBase);
    Addr cTail = std::min(wTail, mTail);

    for (Addr i = cBase; i < cTail; ++i) {
        data[i - mBase] = pktData[i - wBase];
    }

    // also overwrite the WTData
    testAndWrite(m_PhysicalAddress, m_WTData, pkt);

    return cBase < cTail;
}

} // namespace ruby
} // namespace gem5