commit 3d4e412694359f826757b0ca71dea184ff00b457
author Andrea Mondelli <Andrea.Mondelli@ucf.edu> Tue Apr 16 09:35:32 2019 -0400
committer Andrea Mondelli <Andrea.Mondelli@ucf.edu> Tue Apr 16 14:36:14 2019 +0000
tree 751dcc9132bc0bcead27ec1f66fa08be6c5063a8
parent f9e833b1aba5642df9411fdc5e1ee11456cc6d61

mem: missing override specifier

Change-Id: Ied4817bcda317826303a1bb688b41823b18b489b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/18128
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

src/mem/simple_mem.hh

diff --git a/src/mem/simple_mem.hh b/src/mem/simple_mem.hh
index dda4aed..bb11268 100644
--- a/src/mem/simple_mem.hh
+++ b/src/mem/simple_mem.hh
@@ -97,7 +97,7 @@
         void recvFunctional(PacketPtr pkt) override;
         bool recvTimingReq(PacketPtr pkt) override;
         void recvRespRetry() override;
-        AddrRangeList getAddrRanges() const;
+        AddrRangeList getAddrRanges() const override;
     };
 
     MemoryPort port;