commit 3edfacea9c30b0f1c38c3296e7e4110251a247a5
author Ciro Santilli <ciro.santilli@arm.com> Tue Aug 27 15:17:24 2019 +0100
committer Ciro Santilli <ciro.santilli@arm.com> Wed Sep 04 12:33:08 2019 +0000
tree 4d97391a5c1ad01afe8d5d795d3693277a084322
parent bdb327295261dae9e155b2a88b6923c66a939ccd

cpu: reset byte_enable across writeMem calls

data_write_req byteEnable which is used in ARM SVE partial writes was not
being zeroed between writes.

As a result, non-SVE memory write instructions such as STP that followed
SVE memory write instructions could still have the write mask active.

This could lead to wrong simulation behaviour, and to an assertion failure:

src/mem/packet.hh:1211: void Packet::writeData(uint8_t*) const: Assertion
`req->getByteEnable().size() == getSize()' failed. '`

Change-Id: I74b5a82675e9923b0ffdf2c1dd9afb00c91cb204
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20448
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

src/cpu/simple/atomic.cc

diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc
index aa2b641..a873e6d 100644
--- a/src/cpu/simple/atomic.cc
+++ b/src/cpu/simple/atomic.cc
@@ -1,6 +1,6 @@
 /*
  * Copyright 2014 Google, Inc.
- * Copyright (c) 2012-2013,2015,2017-2018 ARM Limited
+ * Copyright (c) 2012-2013,2015,2017-2019 ARM Limited
  * All rights reserved.
  *
  * The license below extends only to copyright in the software and shall
@@ -362,6 +362,7 @@
     } else {
         req->setVirt(0, frag_addr, frag_size, flags, dataMasterId(),
                      inst_addr);
+        req->setByteEnable(std::vector<bool>());
     }
 
     return predicate;