src/cpu/testers/traffic_gen/idle_gen.hh

/*
 * Copyright (c) 2012-2013, 2017-2018 ARM Limited
 * All rights reserved
 *
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 * property including but not limited to intellectual property relating
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 * licensed here under.  You may use the software subject to the license
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 * modified or unmodified, in source code or in binary form.
 *
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 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
 * redistributions in binary form must reproduce the above copyright
 * notice, this list of conditions and the following disclaimer in the
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 * neither the name of the copyright holders nor the names of its
 * contributors may be used to endorse or promote products derived from
 * this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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/**
 * @file
 * Declaration of the idle generator that does nothing.
 */

#ifndef __CPU_TRAFFIC_GEN_IDLE_GEN_HH__
#define __CPU_TRAFFIC_GEN_IDLE_GEN_HH__

#include "base/bitfield.hh"
#include "base/intmath.hh"
#include "base_gen.hh"
#include "mem/packet.hh"

/**
 * The idle generator does nothing.
 */
class IdleGen : public BaseGen
{

  public:

    IdleGen(SimObject &obj, RequestorID requestor_id, Tick _duration)
        : BaseGen(obj, requestor_id, _duration)
    { }

    void enter();

    PacketPtr getNextPacket();

    Tick nextPacketTick(bool elastic, Tick delay) const ;
};

#endif