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/*
* Copyright (c) 2012-2013, 2017-2018 ARM Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
* not be construed as granting a license to any other intellectual
* property including but not limited to intellectual property relating
* to a hardware implementation of the functionality of the software
* licensed here under. You may use the software subject to the license
* terms below provided that you ensure that this notice is replicated
* unmodified and in its entirety in all distributions of the software,
* modified or unmodified, in source code or in binary form.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are
* met: redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer;
* redistributions in binary form must reproduce the above copyright
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* neither the name of the copyright holders nor the names of its
* contributors may be used to endorse or promote products derived from
* this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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*/
/**
* @file
* Declaration of the linear generator that generates sequential
* requests.
*/
#ifndef __CPU_TRAFFIC_GEN_LINEAR_GEN_HH__
#define __CPU_TRAFFIC_GEN_LINEAR_GEN_HH__
#include "base/bitfield.hh"
#include "base/intmath.hh"
#include "base_gen.hh"
#include "mem/packet.hh"
/**
* The linear generator generates sequential requests from a
* start to an end address, with a fixed block size. A
* fraction of the requests are reads, as determined by the
* read percent. There is an optional data limit for when to
* stop generating new requests.
*/
class LinearGen : public StochasticGen
{
public:
/**
* Create a linear address sequence generator. Set
* min_period == max_period for a fixed inter-transaction
* time.
*
* @param obj SimObject owning this sequence generator
* @param requestor_id RequestorID related to the memory requests
* @param _duration duration of this state before transitioning
* @param start_addr Start address
* @param end_addr End address
* @param _blocksize Size used for transactions injected
* @param cacheline_size cache line size in the system
* @param min_period Lower limit of random inter-transaction time
* @param max_period Upper limit of random inter-transaction time
* @param read_percent Percent of transactions that are reads
* @param data_limit Upper limit on how much data to read/write
*/
LinearGen(SimObject &obj,
RequestorID requestor_id, Tick _duration,
Addr start_addr, Addr end_addr,
Addr _blocksize, Addr cacheline_size,
Tick min_period, Tick max_period,
uint8_t read_percent, Addr data_limit)
: StochasticGen(obj, requestor_id, _duration, start_addr, end_addr,
_blocksize, cacheline_size, min_period, max_period,
read_percent, data_limit),
nextAddr(0),
dataManipulated(0)
{ }
void enter();
PacketPtr getNextPacket();
Tick nextPacketTick(bool elastic, Tick delay) const;
private:
/** Address of next request */
Addr nextAddr;
/**
* Counter to determine the amount of data
* manipulated. Used to determine if we should continue
* generating requests.
*/
Addr dataManipulated;
};
#endif