commit 424b946d160b46443c500008122cf50b52153f5d
author Bobby R. Bruce <bbruce@ucdavis.edu> Fri May 27 18:04:48 2022 -0700
committer Bobby Bruce <bbruce@ucdavis.edu> Wed Jun 01 17:41:36 2022 +0000
tree b730cc8e8e8f9fb8986d6dc8cc5162c541c64660
parent d7f5b705760199b38a80d89d9b787ba586737e43

stdlib: Fix LupvBoard to inherit from AbstractSystemBoard

In this patch:
https://gem5-review.googlesource.com/c/public/gem5/+/58909, the
AbstractBoard was refactored. While all otherboards were updated
correctly, the LupvBoard was not. This caused the nightly tests to
fail: https://jenkins.gem5.org/job/nightly/240

This patch corrects this issue.

Change-Id: Icac39d48358daf4acb2f7077f5d3e8871320812e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/60095
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>

src/python/gem5/components/boards/experimental/lupv_board.py

diff --git a/src/python/gem5/components/boards/experimental/lupv_board.py b/src/python/gem5/components/boards/experimental/lupv_board.py
index 52fc1c8..59eedd8 100644
--- a/src/python/gem5/components/boards/experimental/lupv_board.py
+++ b/src/python/gem5/components/boards/experimental/lupv_board.py
@@ -28,7 +28,7 @@
 from typing import List
 
 from ....utils.override import overrides
-from ..abstract_board import AbstractBoard
+from ..abstract_system_board import AbstractSystemBoard
 from ...processors.abstract_processor import AbstractProcessor
 from ...memory.abstract_memory_system import AbstractMemorySystem
 from ...cachehierarchies.abstract_cache_hierarchy import AbstractCacheHierarchy
@@ -72,7 +72,7 @@
     FdtState,
 )
 
-class LupvBoard(AbstractBoard, KernelDiskWorkload):
+class LupvBoard(AbstractSystemBoard, KernelDiskWorkload):
     """
     A board capable of full system simulation for RISC-V.
     This board uses a set of LupIO education-friendly devices.
@@ -100,7 +100,7 @@
 
         super().__init__(clk_freq, processor, memory, cache_hierarchy)
 
-    @overrides(AbstractBoard)
+    @overrides(AbstractSystemBoard)
     def _setup_board(self) -> None:
 
         self.workload = RiscvLinux()
@@ -245,22 +245,22 @@
                 uncacheable=uncacheable_range
             )
 
-    @overrides(AbstractBoard)
+    @overrides(AbstractSystemBoard)
     def has_dma_ports(self) -> bool:
         return False
 
-    @overrides(AbstractBoard)
+    @overrides(AbstractSystemBoard)
     def get_dma_ports(self) -> List[Port]:
         raise NotImplementedError(
             "The LupvBoard does not have DMA Ports. "
             "Use `has_dma_ports()` to check this."
         )
 
-    @overrides(AbstractBoard)
+    @overrides(AbstractSystemBoard)
     def has_io_bus(self) -> bool:
         return True
 
-    @overrides(AbstractBoard)
+    @overrides(AbstractSystemBoard)
     def get_io_bus(self) -> IOXBar:
         return self.iobus
 
@@ -270,7 +270,7 @@
     def get_mem_side_coherent_io_port(self) -> Port:
         return self.iobus.mem_side_ports
 
-    @overrides(AbstractBoard)
+    @overrides(AbstractSystemBoard)
     def _setup_memory_ranges(self):
         memory = self.get_memory()
         mem_size = memory.get_size()