src/arch/riscv/RiscvTLB.py

# -*- mode:python -*-

# Copyright (c) 2007 MIPS Technologies, Inc.
# Copyright (c) 2020 Barkhausen Institut
# Copyright (c) 2021 Huawei International
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from m5.params import *
from m5.proxy import *

from m5.objects.BaseTLB import BaseTLB
from m5.objects.ClockedObject import ClockedObject

class RiscvPagetableWalker(ClockedObject):
    type = 'RiscvPagetableWalker'
    cxx_class = 'gem5::RiscvISA::Walker'
    cxx_header = 'arch/riscv/pagetable_walker.hh'

    port = RequestPort("Port for the hardware table walker")
    system = Param.System(Parent.any, "system object")
    num_squash_per_cycle = Param.Unsigned(4,
            "Number of outstanding walks that can be squashed per cycle")
    # Grab the pma_checker from the MMU
    pma_checker = Param.PMAChecker(Parent.any, "PMA Checker")
    pmp = Param.PMP(Parent.any, "PMP")

class RiscvTLB(BaseTLB):
    type = 'RiscvTLB'
    cxx_class = 'gem5::RiscvISA::TLB'
    cxx_header = 'arch/riscv/tlb.hh'

    size = Param.Int(64, "TLB size")
    walker = Param.RiscvPagetableWalker(\
            RiscvPagetableWalker(), "page table walker")
    # Grab the pma_checker from the MMU
    pma_checker = Param.PMAChecker(Parent.any, "PMA Checker")
    pmp  = Param.PMP(Parent.any, "Physical Memory Protection Unit")