arch,sim: Merge initCPU into the ISA System classes.
Those classes are already ISA specific, so we can just move initCPU's
contents there and take it out of utility.hh, utility.cc, and the base
System's initState.
Change-Id: I28f0d0b50d83efe5116b0b24d20f8182a02823e7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24905
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
diff --git a/src/arch/alpha/ev5.cc b/src/arch/alpha/ev5.cc
index 4e2420d..3613d30 100644
--- a/src/arch/alpha/ev5.cc
+++ b/src/arch/alpha/ev5.cc
@@ -63,26 +63,6 @@
////////////////////////////////////////////////////////////////////////
//
-// Machine dependent functions
-//
-void
-initCPU(ThreadContext *tc, int cpuId)
-{
- initIPRs(tc, cpuId);
-
- tc->setIntReg(16, cpuId);
- tc->setIntReg(0, cpuId);
-
- Addr base = tc->readMiscRegNoEffect(IPR_PAL_BASE);
- Addr offset = ResetFault().vect();
-
- tc->pcState(base + offset);
-
- tc->activate();
-}
-
-////////////////////////////////////////////////////////////////////////
-//
//
//
void
diff --git a/src/arch/alpha/system.cc b/src/arch/alpha/system.cc
index ca4551f..f491b11 100644
--- a/src/arch/alpha/system.cc
+++ b/src/arch/alpha/system.cc
@@ -34,6 +34,7 @@
#include <sys/signal.h>
#include "arch/alpha/ev5.hh"
+#include "arch/alpha/faults.hh"
#include "arch/vtophys.hh"
#include "base/loader/object_file.hh"
#include "base/loader/symtab.hh"
@@ -108,6 +109,21 @@
// Call the initialisation of the super class
System::initState();
+ for (auto *tc: threadContexts) {
+ int cpuId = tc->contextId();
+ initIPRs(tc, cpuId);
+
+ tc->setIntReg(16, cpuId);
+ tc->setIntReg(0, cpuId);
+
+ Addr base = tc->readMiscRegNoEffect(IPR_PAL_BASE);
+ Addr offset = ResetFault().vect();
+
+ tc->pcState(base + offset);
+
+ tc->activate();
+ }
+
// Load program sections into memory
pal->buildImage().mask(loadAddrMask).write(physProxy);
console->buildImage().mask(loadAddrMask).write(physProxy);
diff --git a/src/arch/alpha/utility.hh b/src/arch/alpha/utility.hh
index a0f70a3..ae63f1b 100644
--- a/src/arch/alpha/utility.hh
+++ b/src/arch/alpha/utility.hh
@@ -87,7 +87,6 @@
{ return (addr + PageBytes - 1) & ~(PageBytes - 1); }
void initIPRs(ThreadContext *tc, int cpuId);
-void initCPU(ThreadContext *tc, int cpuId);
void copyRegs(ThreadContext *src, ThreadContext *dest);
diff --git a/src/arch/arm/system.cc b/src/arch/arm/system.cc
index 5c32059..61cc5c3 100644
--- a/src/arch/arm/system.cc
+++ b/src/arch/arm/system.cc
@@ -44,6 +44,7 @@
#include <iostream>
+#include "arch/arm/faults.hh"
#include "arch/arm/semihosting.hh"
#include "base/loader/object_file.hh"
#include "base/loader/symtab.hh"
@@ -136,6 +137,15 @@
// Call the initialisation of the super class
System::initState();
+ // Reset CP15?? What does that mean -- ali
+
+ // FPEXC.EN = 0
+
+ for (auto *tc: threadContexts) {
+ Reset().invoke(tc);
+ tc->activate();
+ }
+
const Params* p = params();
if (bootldr) {
diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc
index 627fc53..e8ca13d 100644
--- a/src/arch/arm/utility.cc
+++ b/src/arch/arm/utility.cc
@@ -52,18 +52,8 @@
#include "mem/fs_translating_port_proxy.hh"
#include "sim/full_system.hh"
-namespace ArmISA {
-
-void
-initCPU(ThreadContext *tc, int cpuId)
+namespace ArmISA
{
- // Reset CP15?? What does that mean -- ali
-
- // FPEXC.EN = 0
-
- Reset().invoke(tc);
- tc->activate();
-}
uint64_t
getArgument(ThreadContext *tc, int &number, uint16_t size, bool fp)
diff --git a/src/arch/arm/utility.hh b/src/arch/arm/utility.hh
index d209664..e70056d 100644
--- a/src/arch/arm/utility.hh
+++ b/src/arch/arm/utility.hh
@@ -103,8 +103,6 @@
panic("Copy Misc. Regs Not Implemented Yet\n");
}
-void initCPU(ThreadContext *tc, int cpuId);
-
/** Send an event (SEV) to a specific PE if there isn't
* already a pending event */
void sendEvent(ThreadContext *tc);
diff --git a/src/arch/mips/utility.cc b/src/arch/mips/utility.cc
index a98b58e..fe06ca1 100644
--- a/src/arch/mips/utility.cc
+++ b/src/arch/mips/utility.cc
@@ -218,12 +218,6 @@
}
void
-initCPU(ThreadContext *tc, int cpuId)
-{
- tc->activate();
-}
-
-void
copyRegs(ThreadContext *src, ThreadContext *dest)
{
// First loop through the integer registers.
diff --git a/src/arch/mips/utility.hh b/src/arch/mips/utility.hh
index 67fe3a4..3338550 100644
--- a/src/arch/mips/utility.hh
+++ b/src/arch/mips/utility.hh
@@ -93,17 +93,15 @@
//
inline Addr
TruncPage(Addr addr)
-{ return addr & ~(PageBytes - 1); }
+{
+ return addr & ~(PageBytes - 1);
+}
inline Addr
RoundPage(Addr addr)
-{ return (addr + PageBytes - 1) & ~(PageBytes - 1); }
-
-////////////////////////////////////////////////////////////////////////
-//
-// CPU Utility
-//
-void initCPU(ThreadContext *tc, int cpuId);
+{
+ return (addr + PageBytes - 1) & ~(PageBytes - 1);
+}
void copyRegs(ThreadContext *src, ThreadContext *dest);
void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
diff --git a/src/arch/null/utility.hh b/src/arch/null/utility.hh
index 69055c7..f1e347d 100644
--- a/src/arch/null/utility.hh
+++ b/src/arch/null/utility.hh
@@ -52,8 +52,6 @@
return 0;
}
-inline void initCPU(ThreadContext *tc, int cpuId) {}
-
}
#endif // __ARCH_NULL_UTILITY_HH__
diff --git a/src/arch/power/utility.cc b/src/arch/power/utility.cc
index 6738c12..3186921 100644
--- a/src/arch/power/utility.cc
+++ b/src/arch/power/utility.cc
@@ -72,11 +72,4 @@
panic("Not Implemented for POWER");
}
-void
-initCPU(ThreadContext *tc, int cpuId)
-{
- panic("initCPU not implemented for POWER.\n");
-}
-
-
} // namespace PowerISA
diff --git a/src/arch/power/utility.hh b/src/arch/power/utility.hh
index 3ae1d82..ce0f4ea 100644
--- a/src/arch/power/utility.hh
+++ b/src/arch/power/utility.hh
@@ -78,8 +78,6 @@
return 0;
}
-void initCPU(ThreadContext *, int cpuId);
-
} // namespace PowerISA
diff --git a/src/arch/riscv/SConscript b/src/arch/riscv/SConscript
index 2ddba72..25adb53 100644
--- a/src/arch/riscv/SConscript
+++ b/src/arch/riscv/SConscript
@@ -57,7 +57,6 @@
Source('stacktrace.cc')
Source('tlb.cc')
Source('system.cc')
- Source('utility.cc')
Source('linux/process.cc')
Source('linux/linux.cc')
diff --git a/src/arch/riscv/bare_metal/system.cc b/src/arch/riscv/bare_metal/system.cc
index 44e14e5..8d4ea41 100644
--- a/src/arch/riscv/bare_metal/system.cc
+++ b/src/arch/riscv/bare_metal/system.cc
@@ -30,6 +30,7 @@
#include "arch/riscv/bare_metal/system.hh"
+#include "arch/riscv/faults.hh"
#include "base/loader/object_file.hh"
BareMetalRiscvSystem::BareMetalRiscvSystem(Params *p)
@@ -54,6 +55,11 @@
// Call the initialisation of the super class
RiscvSystem::initState();
+ for (auto *tc: threadContexts) {
+ RiscvISA::Reset().invoke(tc);
+ tc->activate();
+ }
+
// load program sections into memory
if (!bootloader->buildImage().write(physProxy)) {
warn("could not load sections to memory");
diff --git a/src/arch/riscv/utility.cc b/src/arch/riscv/utility.cc
deleted file mode 100644
index 949d7c6..0000000
--- a/src/arch/riscv/utility.cc
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * Copyright (c) 2018 TU Dresden
- * All rights reserved
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are
- * met: redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer;
- * redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution;
- * neither the name of the copyright holders nor the names of its
- * contributors may be used to endorse or promote products derived from
- * this software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Authors: Robert Scheffel
- */
-
-#include "arch/riscv/utility.hh"
-
-#include "arch/riscv/faults.hh"
-
-namespace RiscvISA
-{
-
-void initCPU(ThreadContext *tc, int cpuId)
-{
- Reset().invoke(tc);
- tc->activate();
-}
-
-}
diff --git a/src/arch/riscv/utility.hh b/src/arch/riscv/utility.hh
index f6e1f34..1b8e2d9 100644
--- a/src/arch/riscv/utility.hh
+++ b/src/arch/riscv/utility.hh
@@ -181,11 +181,6 @@
return 0;
}
-/**
- * init Cpu function
- */
-void initCPU(ThreadContext *tc, int cpuId);
-
} // namespace RiscvISA
#endif // __ARCH_RISCV_UTILITY_HH__
diff --git a/src/arch/sparc/system.cc b/src/arch/sparc/system.cc
index 1a809be..1a495cc 100644
--- a/src/arch/sparc/system.cc
+++ b/src/arch/sparc/system.cc
@@ -30,6 +30,7 @@
#include "arch/sparc/system.hh"
+#include "arch/sparc/faults.hh"
#include "arch/vtophys.hh"
#include "base/loader/object_file.hh"
#include "base/loader/symtab.hh"
@@ -154,6 +155,14 @@
// @todo any fixup code over writing data in binaries on setting break
// events on functions should happen here.
+
+ if (threadContexts.empty())
+ return;
+
+ // Other CPUs will get activated by IPIs.
+ auto *tc = threadContexts[0];
+ SparcISA::PowerOnReset().invoke(tc);
+ tc->activate();
}
SparcSystem::~SparcSystem()
diff --git a/src/arch/sparc/utility.cc b/src/arch/sparc/utility.cc
index 245f455..e1ae563 100644
--- a/src/arch/sparc/utility.cc
+++ b/src/arch/sparc/utility.cc
@@ -253,16 +253,4 @@
tc->pcState(newPC);
}
-
-void
-initCPU(ThreadContext *tc, int cpuId)
-{
- // Other CPUs will get activated by IPIs.
- if (cpuId != 0)
- return;
-
- PowerOnReset().invoke(tc);
- tc->activate();
-}
-
} // namespace SPARC_ISA
diff --git a/src/arch/sparc/utility.hh b/src/arch/sparc/utility.hh
index 74e0c11..6318b43 100644
--- a/src/arch/sparc/utility.hh
+++ b/src/arch/sparc/utility.hh
@@ -62,8 +62,6 @@
return !(pstate.priv || hpstate.hpriv);
}
-void initCPU(ThreadContext *tc, int cpuId);
-
void copyRegs(ThreadContext *src, ThreadContext *dest);
void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
diff --git a/src/arch/x86/system.cc b/src/arch/x86/system.cc
index 096f10f..b0dab7b 100644
--- a/src/arch/x86/system.cc
+++ b/src/arch/x86/system.cc
@@ -43,6 +43,7 @@
#include "arch/x86/bios/intelmp.hh"
#include "arch/x86/bios/smbios.hh"
+#include "arch/x86/faults.hh"
#include "arch/x86/isa_traits.hh"
#include "base/loader/object_file.hh"
#include "cpu/thread_context.hh"
@@ -107,6 +108,19 @@
{
System::initState();
+ for (auto *tc: threadContexts) {
+ X86ISA::InitInterrupt(0).invoke(tc);
+
+ if (tc->contextId() == 0) {
+ tc->activate();
+ } else {
+ // This is an application processor (AP). It should be initialized
+ // to look like only the BIOS POST has run on it and put then put
+ // it into a halted state.
+ tc->suspend();
+ }
+ }
+
if (!kernel)
fatal("No kernel to load.\n");
diff --git a/src/arch/x86/utility.cc b/src/arch/x86/utility.cc
index 21765ce..6f91a17 100644
--- a/src/arch/x86/utility.cc
+++ b/src/arch/x86/utility.cc
@@ -72,21 +72,6 @@
}
void
-initCPU(ThreadContext *tc, int cpuId)
-{
- InitInterrupt(0).invoke(tc);
-
- if (cpuId == 0) {
- tc->activate();
- } else {
- // This is an application processor (AP). It should be initialized to
- // look like only the BIOS POST has run on it and put then put it into
- // a halted state.
- tc->suspend();
- }
-}
-
-void
copyMiscRegs(ThreadContext *src, ThreadContext *dest)
{
// This function assumes no side effects other than TLB invalidation
diff --git a/src/arch/x86/utility.hh b/src/arch/x86/utility.hh
index 88c7a17..7559b4b 100644
--- a/src/arch/x86/utility.hh
+++ b/src/arch/x86/utility.hh
@@ -69,8 +69,6 @@
}
}
- void initCPU(ThreadContext *tc, int cpuId);
-
void copyRegs(ThreadContext *src, ThreadContext *dest);
void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
diff --git a/src/sim/system.cc b/src/sim/system.cc
index 368eb54..b5b59ef 100644
--- a/src/sim/system.cc
+++ b/src/sim/system.cc
@@ -349,8 +349,6 @@
System::initState()
{
if (FullSystem) {
- for (auto *tc: threadContexts)
- TheISA::initCPU(tc, tc->contextId());
// Moved from the constructor to here since it relies on the
// address map being resolved in the interconnect
/**
