commit 4f6b8f1d7108e0af786bbcbac24487b5e05c0cd1
author Giacomo Travaglini <giacomo.travaglini@arm.com> Fri Mar 20 19:41:29 2020 +0000
committer Giacomo Travaglini <giacomo.travaglini@arm.com> Mon Mar 30 15:54:56 2020 +0000
tree 44768aefacd7cc0d53fa7c2517301036db608c52
parent ae69a12b3bd40bc86997c96cac9239f2f973aa95

dev-arm: Fix pci_mem_base setting in VExpress_GEM5_Base

This was not actually used and DTB was generated using an hardcoded
value.

Change-Id: Ie8fd63495df5cb56418593cf0dd5432dc2992eac
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27288
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>

src/dev/arm/RealView.py

diff --git a/src/dev/arm/RealView.py b/src/dev/arm/RealView.py
index 43d2b15..cf57ee2 100644
--- a/src/dev/arm/RealView.py
+++ b/src/dev/arm/RealView.py
@@ -160,7 +160,7 @@
 
         # AXI memory address range
         ranges += self.pciFdtAddr(space=2, addr=0)
-        ranges += state.addrCells(0x40000000) # Fixed offset
+        ranges += state.addrCells(self.pci_mem_base)
         ranges += local_state.sizeCells(0x40000000) # Fixed size
         node.append(FdtPropertyWords("ranges", ranges))
 
@@ -1025,6 +1025,7 @@
     pci_host = GenericArmPciHost(
         conf_base=0x30000000, conf_size='256MB', conf_device_bits=12,
         pci_pio_base=0x2f000000,
+        pci_mem_base=0x40000000,
         int_policy="ARM_PCI_INT_DEV", int_base=100, int_count=4)
 
     energy_ctrl = EnergyCtrl(pio_addr=0x10000000)