commit 5084b90e2af6e5bfad3119b4431a3b063ef3b799
author Andrea Mondelli <Andrea.Mondelli@ucf.edu> Mon Mar 25 12:41:54 2019 -0400
committer Andrea Mondelli <Andrea.Mondelli@ucf.edu> Wed Apr 03 16:48:55 2019 +0000
tree fa013c4f0e55cc67ed8746d72173619230fb1b99
parent 5caa4517345d4833af44e510f78717ee7e0ad8d4

arch-mips: added missing override specifier (o3)

Change-Id: Ic538825a2964fd62def672b933a83067a15bd12a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17648
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

src/cpu/o3/dyn_inst.hh

diff --git a/src/cpu/o3/dyn_inst.hh b/src/cpu/o3/dyn_inst.hh
index 640ebf8..24c59a2 100644
--- a/src/cpu/o3/dyn_inst.hh
+++ b/src/cpu/o3/dyn_inst.hh
@@ -432,14 +432,14 @@
 
 #if THE_ISA == MIPS_ISA
     RegVal
-    readRegOtherThread(const RegId& misc_reg, ThreadID tid)
+    readRegOtherThread(const RegId& misc_reg, ThreadID tid) override
     {
         panic("MIPS MT not defined for O3 CPU.\n");
         return 0;
     }
 
     void
-    setRegOtherThread(const RegId& misc_reg, RegVal val, ThreadID tid)
+    setRegOtherThread(const RegId& misc_reg, RegVal val, ThreadID tid) override
     {
         panic("MIPS MT not defined for O3 CPU.\n");
     }