commit 51022bfe0eeaef5f08d6ace98ebfb1917d1b3331
author Giacomo Travaglini <giacomo.travaglini@arm.com> Tue Aug 20 13:53:39 2019 +0100
committer Giacomo Travaglini <giacomo.travaglini@arm.com> Fri Sep 06 11:53:49 2019 +0000
tree 1f25bf357a5527834c9189fb9e33f7ecfd802b77
parent 7a1f018ce77e5c1b56c241d4899aa454fc168366

dev-arm: Add GICv3 unimplemented Hyp Active Priorities Group regs

ICH_APxR1, ICH_APxR2, ICH_APxR3 are implemented only if supporting more
than 6 bits of priority. Since this is not the case, they are currently
unimplemented.
According to spec, unimplemented registers are RAZ/WI.

Change-Id: Ifd7f7a3d42b4575c2f7aff3b95d5a47ac1e61842
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20619
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

src/dev/arm/gic_v3_cpu_interface.cc

diff --git a/src/dev/arm/gic_v3_cpu_interface.cc b/src/dev/arm/gic_v3_cpu_interface.cc
index c6c1b14..b8752dd 100644
--- a/src/dev/arm/gic_v3_cpu_interface.cc
+++ b/src/dev/arm/gic_v3_cpu_interface.cc
@@ -675,11 +675,35 @@
       case MISCREG_ICH_AP0R0_EL2:
         break;
 
+      // only implemented if supporting 6 or more bits of priority
+      case MISCREG_ICH_AP0R1:
+      case MISCREG_ICH_AP0R1_EL2:
+      // only implemented if supporting 7 or more bits of priority
+      case MISCREG_ICH_AP0R2:
+      case MISCREG_ICH_AP0R2_EL2:
+      // only implemented if supporting 7 or more bits of priority
+      case MISCREG_ICH_AP0R3:
+      case MISCREG_ICH_AP0R3_EL2:
+        // Unimplemented registers are RAZ/WI
+        return 0;
+
       // Hyp Active Priorities Group 1 Registers
       case MISCREG_ICH_AP1R0:
       case MISCREG_ICH_AP1R0_EL2:
         break;
 
+      // only implemented if supporting 6 or more bits of priority
+      case MISCREG_ICH_AP1R1:
+      case MISCREG_ICH_AP1R1_EL2:
+      // only implemented if supporting 7 or more bits of priority
+      case MISCREG_ICH_AP1R2:
+      case MISCREG_ICH_AP1R2_EL2:
+      // only implemented if supporting 7 or more bits of priority
+      case MISCREG_ICH_AP1R3:
+      case MISCREG_ICH_AP1R3_EL2:
+        // Unimplemented registers are RAZ/WI
+        return 0;
+
       // Maintenance Interrupt State Register
       case MISCREG_ICH_MISR:
       case MISCREG_ICH_MISR_EL2:
@@ -1614,13 +1638,39 @@
       }
 
       // Hyp Active Priorities Group 0 Registers
-      case MISCREG_ICH_AP0R0 ... MISCREG_ICH_AP0R3:
-      case MISCREG_ICH_AP0R0_EL2 ... MISCREG_ICH_AP0R3_EL2:
-      // Hyp Active Priorities Group 1 Registers
-      case MISCREG_ICH_AP1R0 ... MISCREG_ICH_AP1R3:
-      case MISCREG_ICH_AP1R0_EL2 ... MISCREG_ICH_AP1R3_EL2:
+      case MISCREG_ICH_AP0R0:
+      case MISCREG_ICH_AP0R0_EL2:
         break;
 
+      // only implemented if supporting 6 or more bits of priority
+      case MISCREG_ICH_AP0R1:
+      case MISCREG_ICH_AP0R1_EL2:
+      // only implemented if supporting 7 or more bits of priority
+      case MISCREG_ICH_AP0R2:
+      case MISCREG_ICH_AP0R2_EL2:
+      // only implemented if supporting 7 or more bits of priority
+      case MISCREG_ICH_AP0R3:
+      case MISCREG_ICH_AP0R3_EL2:
+        // Unimplemented registers are RAZ/WI
+        return;
+
+      // Hyp Active Priorities Group 1 Registers
+      case MISCREG_ICH_AP1R0:
+      case MISCREG_ICH_AP1R0_EL2:
+        break;
+
+      // only implemented if supporting 6 or more bits of priority
+      case MISCREG_ICH_AP1R1:
+      case MISCREG_ICH_AP1R1_EL2:
+      // only implemented if supporting 7 or more bits of priority
+      case MISCREG_ICH_AP1R2:
+      case MISCREG_ICH_AP1R2_EL2:
+      // only implemented if supporting 7 or more bits of priority
+      case MISCREG_ICH_AP1R3:
+      case MISCREG_ICH_AP1R3_EL2:
+        // Unimplemented registers are RAZ/WI
+        return;
+
       default:
         panic("Gicv3CPUInterface::setMiscReg(): unknown register %d (%s)",
               misc_reg, miscRegName[misc_reg]);