mem: Reverse order of write/read mem queue check
For atomic RMW instructions that go directly to memory, we want to put
them on the write queue instead of the read queue. Swap the if/else
condition to accomplish this.
Note: This is ignoring the read latency of the RMW, but these
instructions should usually be handled in caches anyway.
Change-Id: I62dbfff3a16ac470f1ebdb489abe878962b20bb6
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17828
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
diff --git a/src/mem/dram_ctrl.cc b/src/mem/dram_ctrl.cc
index dd03cf1..e89a47a 100644
--- a/src/mem/dram_ctrl.cc
+++ b/src/mem/dram_ctrl.cc
@@ -644,21 +644,7 @@
qosSchedule( { &readQueue, &writeQueue }, burstSize, pkt);
// check local buffers and do not accept if full
- if (pkt->isRead()) {
- assert(size != 0);
- if (readQueueFull(dram_pkt_count)) {
- DPRINTF(DRAM, "Read queue full, not accepting\n");
- // remember that we have to retry this port
- retryRdReq = true;
- numRdRetry++;
- return false;
- } else {
- addToReadQueue(pkt, dram_pkt_count);
- readReqs++;
- bytesReadSys += size;
- }
- } else {
- assert(pkt->isWrite());
+ if (pkt->isWrite()) {
assert(size != 0);
if (writeQueueFull(dram_pkt_count)) {
DPRINTF(DRAM, "Write queue full, not accepting\n");
@@ -671,6 +657,20 @@
writeReqs++;
bytesWrittenSys += size;
}
+ } else {
+ assert(pkt->isRead());
+ assert(size != 0);
+ if (readQueueFull(dram_pkt_count)) {
+ DPRINTF(DRAM, "Read queue full, not accepting\n");
+ // remember that we have to retry this port
+ retryRdReq = true;
+ numRdRetry++;
+ return false;
+ } else {
+ addToReadQueue(pkt, dram_pkt_count);
+ readReqs++;
+ bytesReadSys += size;
+ }
}
return true;