commit | 52c777bbee535fb30774069c038fc3d614eebaee | [log] [tgz] |
---|---|---|
author | Nikos Nikoleris <nikos.nikoleris@arm.com> | Thu Apr 23 20:03:34 2020 +0100 |
committer | Nikos Nikoleris <nikos.nikoleris@arm.com> | Thu Apr 30 09:14:42 2020 +0000 |
tree | 10c2711f95f48469669781119344634870852d78 | |
parent | 880496b35e88fddaefe6f62350c2dfa987b2dee9 [diff] |
mem-ruby: Avoid const from member due to &Message::operator=(...) Change-Id: I172f48ce8ee4a3870165309342dadc2ac39ded9a Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com> Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28249 Reviewed-by: Matthew Poremba <matthew.poremba@amd.com> Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu> Tested-by: kokoro <noreply+kokoro@google.com>
diff --git a/src/mem/ruby/slicc_interface/Message.hh b/src/mem/ruby/slicc_interface/Message.hh index 0c2e0aa..1044fe0 100644 --- a/src/mem/ruby/slicc_interface/Message.hh +++ b/src/mem/ruby/slicc_interface/Message.hh
@@ -104,7 +104,7 @@ void setVnet(int net) { vnet = net; } private: - const Tick m_time; + Tick m_time; Tick m_LastEnqueueTime; // my last enqueue time Tick m_DelayedTicks; // my delayed cycles uint64_t m_msg_counter; // FIXME, should this be a 64-bit value?