sim: Allow passing a user-defined L2XBar to addTwoLevelCacheHierarchy().
Before this CL, the addTwoLevelCacheHierarchy() function uses the
default L2XBar class as the interconnect between CPU L1 caches and
L2. This CL allows passing a user-defined bus to overwrite the
default L2XBar by adding an optional argument to the function.
Change-Id: I917657272fd4924ee0bed882a226851afba26847
Reviewed-on: https://gem5-review.googlesource.com/7364
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py
index c100f0e..3e82daf 100644
--- a/src/cpu/BaseCPU.py
+++ b/src/cpu/BaseCPU.py
@@ -299,9 +299,10 @@
self._cached_ports += ["checker.itb.walker.port", \
"checker.dtb.walker.port"]
- def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc = None, dwc = None):
+ def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc=None, dwc=None,
+ xbar=None):
self.addPrivateSplitL1Caches(ic, dc, iwc, dwc)
- self.toL2Bus = L2XBar()
+ self.toL2Bus = xbar if xbar else L2XBar()
self.connectCachedPorts(self.toL2Bus)
self.l2cache = l2c
self.toL2Bus.master = self.l2cache.cpu_side