src/arch/arm/fastmodel/iris/tlb.hh

/*
 * Copyright 2019 Google Inc.
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 * this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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#ifndef __ARCH_ARM_FASTMODEL_IRIS_TLB_HH__
#define __ARCH_ARM_FASTMODEL_IRIS_TLB_HH__

#include "arch/generic/tlb.hh"
#include "params/IrisTLB.hh"

namespace gem5
{

namespace Iris
{

class TLB : public BaseTLB
{
  public:
    PARAMS(IrisTLB)

    TLB(const Params &p) : BaseTLB(p) {}

    void demapPage(Addr vaddr, uint64_t asn) override {}
    void flushAll() override {}
    void takeOverFrom(BaseTLB *otlb) override {}

    Fault translateFunctional(
        const RequestPtr &req, gem5::ThreadContext *tc,
        BaseMMU::Mode mode) override;
    Fault translateAtomic(
        const RequestPtr &req, gem5::ThreadContext *tc,
        BaseMMU::Mode mode) override;
    void translateTiming(
        const RequestPtr &req, gem5::ThreadContext *tc,
        BaseMMU::Translation *translation, BaseMMU::Mode mode) override;

    Fault
    finalizePhysical(
        const RequestPtr &req, gem5::ThreadContext *tc,
        BaseMMU::Mode mode) const override
    {
        return NoFault;
    }
};

} // namespace Iris
} // namespace gem5

#endif // __ARCH_ARM_FASTMODEL_IRIS_TLB_HH__