| |
| ---------- Begin Simulation Statistics ---------- |
| sim_seconds 0.000127 |
| sim_ticks 126524000 |
| final_tick 126524000 |
| sim_freq 1000000000000 |
| host_inst_rate 211101 |
| host_op_rate 211100 |
| host_tick_rate 22855727 |
| host_mem_usage 280860 |
| host_seconds 5.54 |
| sim_insts 1168600 |
| sim_ops 1168600 |
| system.voltage_domain.voltage 1 |
| system.clk_domain.clock 1000 |
| system.physmem.pwrStateResidencyTicks::UNDEFINED 126524000 |
| system.physmem.bytes_read::cpu0.inst 23616 |
| system.physmem.bytes_read::cpu0.data 10816 |
| system.physmem.bytes_read::cpu1.inst 5888 |
| system.physmem.bytes_read::cpu1.data 1344 |
| system.physmem.bytes_read::cpu2.inst 896 |
| system.physmem.bytes_read::cpu2.data 896 |
| system.physmem.bytes_read::cpu3.inst 768 |
| system.physmem.bytes_read::cpu3.data 960 |
| system.physmem.bytes_read::total 45184 |
| system.physmem.bytes_inst_read::cpu0.inst 23616 |
| system.physmem.bytes_inst_read::cpu1.inst 5888 |
| system.physmem.bytes_inst_read::cpu2.inst 896 |
| system.physmem.bytes_inst_read::cpu3.inst 768 |
| system.physmem.bytes_inst_read::total 31168 |
| system.physmem.num_reads::cpu0.inst 369 |
| system.physmem.num_reads::cpu0.data 169 |
| system.physmem.num_reads::cpu1.inst 92 |
| system.physmem.num_reads::cpu1.data 21 |
| system.physmem.num_reads::cpu2.inst 14 |
| system.physmem.num_reads::cpu2.data 14 |
| system.physmem.num_reads::cpu3.inst 12 |
| system.physmem.num_reads::cpu3.data 15 |
| system.physmem.num_reads::total 706 |
| system.physmem.bw_read::cpu0.inst 186652335 |
| system.physmem.bw_read::cpu0.data 85485758 |
| system.physmem.bw_read::cpu1.inst 46536625 |
| system.physmem.bw_read::cpu1.data 10622491 |
| system.physmem.bw_read::cpu2.inst 7081660 |
| system.physmem.bw_read::cpu2.data 7081660 |
| system.physmem.bw_read::cpu3.inst 6069995 |
| system.physmem.bw_read::cpu3.data 7587493 |
| system.physmem.bw_read::total 357118017 |
| system.physmem.bw_inst_read::cpu0.inst 186652335 |
| system.physmem.bw_inst_read::cpu1.inst 46536625 |
| system.physmem.bw_inst_read::cpu2.inst 7081660 |
| system.physmem.bw_inst_read::cpu3.inst 6069995 |
| system.physmem.bw_inst_read::total 246340615 |
| system.physmem.bw_total::cpu0.inst 186652335 |
| system.physmem.bw_total::cpu0.data 85485758 |
| system.physmem.bw_total::cpu1.inst 46536625 |
| system.physmem.bw_total::cpu1.data 10622491 |
| system.physmem.bw_total::cpu2.inst 7081660 |
| system.physmem.bw_total::cpu2.data 7081660 |
| system.physmem.bw_total::cpu3.inst 6069995 |
| system.physmem.bw_total::cpu3.data 7587493 |
| system.physmem.bw_total::total 357118017 |
| system.physmem.readReqs 706 |
| system.physmem.writeReqs 0 |
| system.physmem.readBursts 706 |
| system.physmem.writeBursts 0 |
| system.physmem.bytesReadDRAM 45184 |
| system.physmem.bytesReadWrQ 0 |
| system.physmem.bytesWritten 0 |
| system.physmem.bytesReadSys 45184 |
| system.physmem.bytesWrittenSys 0 |
| system.physmem.servicedByWrQ 0 |
| system.physmem.mergedWrBursts 0 |
| system.physmem.neitherReadNorWriteReqs 0 |
| system.physmem.perBankRdBursts::0 118 |
| system.physmem.perBankRdBursts::1 44 |
| system.physmem.perBankRdBursts::2 34 |
| system.physmem.perBankRdBursts::3 38 |
| system.physmem.perBankRdBursts::4 62 |
| system.physmem.perBankRdBursts::5 39 |
| system.physmem.perBankRdBursts::6 22 |
| system.physmem.perBankRdBursts::7 39 |
| system.physmem.perBankRdBursts::8 11 |
| system.physmem.perBankRdBursts::9 29 |
| system.physmem.perBankRdBursts::10 23 |
| system.physmem.perBankRdBursts::11 13 |
| system.physmem.perBankRdBursts::12 69 |
| system.physmem.perBankRdBursts::13 46 |
| system.physmem.perBankRdBursts::14 19 |
| system.physmem.perBankRdBursts::15 100 |
| system.physmem.perBankWrBursts::0 0 |
| system.physmem.perBankWrBursts::1 0 |
| system.physmem.perBankWrBursts::2 0 |
| system.physmem.perBankWrBursts::3 0 |
| system.physmem.perBankWrBursts::4 0 |
| system.physmem.perBankWrBursts::5 0 |
| system.physmem.perBankWrBursts::6 0 |
| system.physmem.perBankWrBursts::7 0 |
| system.physmem.perBankWrBursts::8 0 |
| system.physmem.perBankWrBursts::9 0 |
| system.physmem.perBankWrBursts::10 0 |
| system.physmem.perBankWrBursts::11 0 |
| system.physmem.perBankWrBursts::12 0 |
| system.physmem.perBankWrBursts::13 0 |
| system.physmem.perBankWrBursts::14 0 |
| system.physmem.perBankWrBursts::15 0 |
| system.physmem.numRdRetry 0 |
| system.physmem.numWrRetry 0 |
| system.physmem.totGap 126284000 |
| system.physmem.readPktSize::0 0 |
| system.physmem.readPktSize::1 0 |
| system.physmem.readPktSize::2 0 |
| system.physmem.readPktSize::3 0 |
| system.physmem.readPktSize::4 0 |
| system.physmem.readPktSize::5 0 |
| system.physmem.readPktSize::6 706 |
| system.physmem.writePktSize::0 0 |
| system.physmem.writePktSize::1 0 |
| system.physmem.writePktSize::2 0 |
| system.physmem.writePktSize::3 0 |
| system.physmem.writePktSize::4 0 |
| system.physmem.writePktSize::5 0 |
| system.physmem.writePktSize::6 0 |
| system.physmem.rdQLenPdf::0 414 |
| system.physmem.rdQLenPdf::1 215 |
| system.physmem.rdQLenPdf::2 55 |
| system.physmem.rdQLenPdf::3 17 |
| system.physmem.rdQLenPdf::4 4 |
| system.physmem.rdQLenPdf::5 1 |
| system.physmem.rdQLenPdf::6 0 |
| system.physmem.rdQLenPdf::7 0 |
| system.physmem.rdQLenPdf::8 0 |
| system.physmem.rdQLenPdf::9 0 |
| system.physmem.rdQLenPdf::10 0 |
| system.physmem.rdQLenPdf::11 0 |
| system.physmem.rdQLenPdf::12 0 |
| system.physmem.rdQLenPdf::13 0 |
| system.physmem.rdQLenPdf::14 0 |
| system.physmem.rdQLenPdf::15 0 |
| system.physmem.rdQLenPdf::16 0 |
| system.physmem.rdQLenPdf::17 0 |
| system.physmem.rdQLenPdf::18 0 |
| system.physmem.rdQLenPdf::19 0 |
| system.physmem.rdQLenPdf::20 0 |
| system.physmem.rdQLenPdf::21 0 |
| system.physmem.rdQLenPdf::22 0 |
| system.physmem.rdQLenPdf::23 0 |
| system.physmem.rdQLenPdf::24 0 |
| system.physmem.rdQLenPdf::25 0 |
| system.physmem.rdQLenPdf::26 0 |
| system.physmem.rdQLenPdf::27 0 |
| system.physmem.rdQLenPdf::28 0 |
| system.physmem.rdQLenPdf::29 0 |
| system.physmem.rdQLenPdf::30 0 |
| system.physmem.rdQLenPdf::31 0 |
| system.physmem.wrQLenPdf::0 0 |
| system.physmem.wrQLenPdf::1 0 |
| system.physmem.wrQLenPdf::2 0 |
| system.physmem.wrQLenPdf::3 0 |
| system.physmem.wrQLenPdf::4 0 |
| system.physmem.wrQLenPdf::5 0 |
| system.physmem.wrQLenPdf::6 0 |
| system.physmem.wrQLenPdf::7 0 |
| system.physmem.wrQLenPdf::8 0 |
| system.physmem.wrQLenPdf::9 0 |
| system.physmem.wrQLenPdf::10 0 |
| system.physmem.wrQLenPdf::11 0 |
| system.physmem.wrQLenPdf::12 0 |
| system.physmem.wrQLenPdf::13 0 |
| system.physmem.wrQLenPdf::14 0 |
| system.physmem.wrQLenPdf::15 0 |
| system.physmem.wrQLenPdf::16 0 |
| system.physmem.wrQLenPdf::17 0 |
| system.physmem.wrQLenPdf::18 0 |
| system.physmem.wrQLenPdf::19 0 |
| system.physmem.wrQLenPdf::20 0 |
| system.physmem.wrQLenPdf::21 0 |
| system.physmem.wrQLenPdf::22 0 |
| system.physmem.wrQLenPdf::23 0 |
| system.physmem.wrQLenPdf::24 0 |
| system.physmem.wrQLenPdf::25 0 |
| system.physmem.wrQLenPdf::26 0 |
| system.physmem.wrQLenPdf::27 0 |
| system.physmem.wrQLenPdf::28 0 |
| system.physmem.wrQLenPdf::29 0 |
| system.physmem.wrQLenPdf::30 0 |
| system.physmem.wrQLenPdf::31 0 |
| system.physmem.wrQLenPdf::32 0 |
| system.physmem.wrQLenPdf::33 0 |
| system.physmem.wrQLenPdf::34 0 |
| system.physmem.wrQLenPdf::35 0 |
| system.physmem.wrQLenPdf::36 0 |
| system.physmem.wrQLenPdf::37 0 |
| system.physmem.wrQLenPdf::38 0 |
| system.physmem.wrQLenPdf::39 0 |
| system.physmem.wrQLenPdf::40 0 |
| system.physmem.wrQLenPdf::41 0 |
| system.physmem.wrQLenPdf::42 0 |
| system.physmem.wrQLenPdf::43 0 |
| system.physmem.wrQLenPdf::44 0 |
| system.physmem.wrQLenPdf::45 0 |
| system.physmem.wrQLenPdf::46 0 |
| system.physmem.wrQLenPdf::47 0 |
| system.physmem.wrQLenPdf::48 0 |
| system.physmem.wrQLenPdf::49 0 |
| system.physmem.wrQLenPdf::50 0 |
| system.physmem.wrQLenPdf::51 0 |
| system.physmem.wrQLenPdf::52 0 |
| system.physmem.wrQLenPdf::53 0 |
| system.physmem.wrQLenPdf::54 0 |
| system.physmem.wrQLenPdf::55 0 |
| system.physmem.wrQLenPdf::56 0 |
| system.physmem.wrQLenPdf::57 0 |
| system.physmem.wrQLenPdf::58 0 |
| system.physmem.wrQLenPdf::59 0 |
| system.physmem.wrQLenPdf::60 0 |
| system.physmem.wrQLenPdf::61 0 |
| system.physmem.wrQLenPdf::62 0 |
| system.physmem.wrQLenPdf::63 0 |
| system.physmem.bytesPerActivate::samples 171 |
| system.physmem.bytesPerActivate::mean 248.140351 |
| system.physmem.bytesPerActivate::gmean 165.969670 |
| system.physmem.bytesPerActivate::stdev 244.268664 |
| system.physmem.bytesPerActivate::0-127 61 35.67% 35.67% |
| system.physmem.bytesPerActivate::128-255 47 27.49% 63.16% |
| system.physmem.bytesPerActivate::256-383 27 15.79% 78.95% |
| system.physmem.bytesPerActivate::384-511 11 6.43% 85.38% |
| system.physmem.bytesPerActivate::512-639 7 4.09% 89.47% |
| system.physmem.bytesPerActivate::640-767 7 4.09% 93.57% |
| system.physmem.bytesPerActivate::768-895 4 2.34% 95.91% |
| system.physmem.bytesPerActivate::896-1023 1 0.58% 96.49% |
| system.physmem.bytesPerActivate::1024-1151 6 3.51% 100.00% |
| system.physmem.bytesPerActivate::total 171 |
| system.physmem.totQLat 12887500 |
| system.physmem.totMemAccLat 26125000 |
| system.physmem.totBusLat 3530000 |
| system.physmem.avgQLat 18254.25 |
| system.physmem.avgBusLat 5000.00 |
| system.physmem.avgMemAccLat 37004.25 |
| system.physmem.avgRdBW 357.12 |
| system.physmem.avgWrBW 0.00 |
| system.physmem.avgRdBWSys 357.12 |
| system.physmem.avgWrBWSys 0.00 |
| system.physmem.peakBW 12800.00 |
| system.physmem.busUtil 2.79 |
| system.physmem.busUtilRead 2.79 |
| system.physmem.busUtilWrite 0.00 |
| system.physmem.avgRdQLen 1.22 |
| system.physmem.avgWrQLen 0.00 |
| system.physmem.readRowHits 525 |
| system.physmem.writeRowHits 0 |
| system.physmem.readRowHitRate 74.36 |
| system.physmem.writeRowHitRate nan |
| system.physmem.avgGap 178872.52 |
| system.physmem.pageHitRate 74.36 |
| system.physmem_0.actEnergy 813960 |
| system.physmem_0.preEnergy 417450 |
| system.physmem_0.readEnergy 2827440 |
| system.physmem_0.writeEnergy 0 |
| system.physmem_0.refreshEnergy 9834240.000000 |
| system.physmem_0.actBackEnergy 6303630 |
| system.physmem_0.preBackEnergy 322080 |
| system.physmem_0.actPowerDownEnergy 38492100 |
| system.physmem_0.prePowerDownEnergy 7873440 |
| system.physmem_0.selfRefreshEnergy 2219340 |
| system.physmem_0.totalEnergy 69103680 |
| system.physmem_0.averagePower 546.166212 |
| system.physmem_0.totalIdleTime 111290750 |
| system.physmem_0.memoryStateTime::IDLE 364500 |
| system.physmem_0.memoryStateTime::REF 4166000 |
| system.physmem_0.memoryStateTime::SREF 6945750 |
| system.physmem_0.memoryStateTime::PRE_PDN 20504750 |
| system.physmem_0.memoryStateTime::ACT 10132500 |
| system.physmem_0.memoryStateTime::ACT_PDN 84410500 |
| system.physmem_1.actEnergy 478380 |
| system.physmem_1.preEnergy 231495 |
| system.physmem_1.readEnergy 2213400 |
| system.physmem_1.writeEnergy 0 |
| system.physmem_1.refreshEnergy 11063520.000000 |
| system.physmem_1.actBackEnergy 5380230 |
| system.physmem_1.preBackEnergy 811200 |
| system.physmem_1.actPowerDownEnergy 30383280 |
| system.physmem_1.prePowerDownEnergy 13088160 |
| system.physmem_1.selfRefreshEnergy 5064960 |
| system.physmem_1.totalEnergy 68714625 |
| system.physmem_1.averagePower 543.091286 |
| system.physmem_1.totalIdleTime 112417500 |
| system.physmem_1.memoryStateTime::IDLE 1635500 |
| system.physmem_1.memoryStateTime::REF 4704000 |
| system.physmem_1.memoryStateTime::SREF 11899500 |
| system.physmem_1.memoryStateTime::PRE_PDN 34081750 |
| system.physmem_1.memoryStateTime::ACT 7573250 |
| system.physmem_1.memoryStateTime::ACT_PDN 66630000 |
| system.pwrStateResidencyTicks::UNDEFINED 126524000 |
| system.cpu0.branchPred.lookups 99156 |
| system.cpu0.branchPred.condPredicted 94556 |
| system.cpu0.branchPred.condIncorrect 1594 |
| system.cpu0.branchPred.BTBLookups 96162 |
| system.cpu0.branchPred.BTBHits 0 |
| system.cpu0.branchPred.BTBCorrect 0 |
| system.cpu0.branchPred.BTBHitPct 0.000000 |
| system.cpu0.branchPred.usedRAS 1175 |
| system.cpu0.branchPred.RASInCorrect 128 |
| system.cpu0.branchPred.indirectLookups 96162 |
| system.cpu0.branchPred.indirectHits 88867 |
| system.cpu0.branchPred.indirectMisses 7295 |
| system.cpu0.branchPredindirectMispredicted 1040 |
| system.cpu_clk_domain.clock 500 |
| system.cpu0.workload.numSyscalls 26 |
| system.cpu0.pwrStateResidencyTicks::ON 126524000 |
| system.cpu0.numCycles 253049 |
| system.cpu0.numWorkItemsStarted 0 |
| system.cpu0.numWorkItemsCompleted 0 |
| system.cpu0.fetch.icacheStallCycles 23270 |
| system.cpu0.fetch.Insts 585438 |
| system.cpu0.fetch.Branches 99156 |
| system.cpu0.fetch.predictedBranches 90042 |
| system.cpu0.fetch.Cycles 194902 |
| system.cpu0.fetch.SquashCycles 3486 |
| system.cpu0.fetch.MiscStallCycles 9 |
| system.cpu0.fetch.PendingTrapStallCycles 2371 |
| system.cpu0.fetch.IcacheWaitRetryStallCycles 8 |
| system.cpu0.fetch.CacheLines 8150 |
| system.cpu0.fetch.IcacheSquashes 854 |
| system.cpu0.fetch.rateDist::samples 222303 |
| system.cpu0.fetch.rateDist::mean 2.633514 |
| system.cpu0.fetch.rateDist::stdev 2.266765 |
| system.cpu0.fetch.rateDist::underflows 0 0.00% 0.00% |
| system.cpu0.fetch.rateDist::0 34223 15.39% 15.39% |
| system.cpu0.fetch.rateDist::1 91924 41.35% 56.75% |
| system.cpu0.fetch.rateDist::2 702 0.32% 57.06% |
| system.cpu0.fetch.rateDist::3 1052 0.47% 57.53% |
| system.cpu0.fetch.rateDist::4 464 0.21% 57.74% |
| system.cpu0.fetch.rateDist::5 87528 39.37% 97.12% |
| system.cpu0.fetch.rateDist::6 631 0.28% 97.40% |
| system.cpu0.fetch.rateDist::7 560 0.25% 97.65% |
| system.cpu0.fetch.rateDist::8 5219 2.35% 100.00% |
| system.cpu0.fetch.rateDist::overflows 0 0.00% 100.00% |
| system.cpu0.fetch.rateDist::min_value 0 |
| system.cpu0.fetch.rateDist::max_value 8 |
| system.cpu0.fetch.rateDist::total 222303 |
| system.cpu0.fetch.branchRate 0.391845 |
| system.cpu0.fetch.rate 2.313536 |
| system.cpu0.decode.IdleCycles 17878 |
| system.cpu0.decode.BlockedCycles 19403 |
| system.cpu0.decode.RunCycles 182453 |
| system.cpu0.decode.UnblockCycles 826 |
| system.cpu0.decode.SquashCycles 1743 |
| system.cpu0.decode.DecodedInsts 566849 |
| system.cpu0.rename.SquashCycles 1743 |
| system.cpu0.rename.IdleCycles 18557 |
| system.cpu0.rename.BlockCycles 1896 |
| system.cpu0.rename.serializeStallCycles 16116 |
| system.cpu0.rename.RunCycles 182592 |
| system.cpu0.rename.UnblockCycles 1399 |
| system.cpu0.rename.RenamedInsts 561565 |
| system.cpu0.rename.IQFullEvents 11 |
| system.cpu0.rename.LQFullEvents 11 |
| system.cpu0.rename.SQFullEvents 925 |
| system.cpu0.rename.RenamedOperands 384271 |
| system.cpu0.rename.RenameLookups 1119475 |
| system.cpu0.rename.int_rename_lookups 845599 |
| system.cpu0.rename.CommittedMaps 365219 |
| system.cpu0.rename.UndoneMaps 19052 |
| system.cpu0.rename.serializingInsts 1117 |
| system.cpu0.rename.tempSerializingInsts 1148 |
| system.cpu0.rename.skidInsts 5501 |
| system.cpu0.memDep0.insertedLoads 179238 |
| system.cpu0.memDep0.insertedStores 90554 |
| system.cpu0.memDep0.conflictingLoads 87434 |
| system.cpu0.memDep0.conflictingStores 87111 |
| system.cpu0.iq.iqInstsAdded 468496 |
| system.cpu0.iq.iqNonSpecInstsAdded 1145 |
| system.cpu0.iq.iqInstsIssued 464441 |
| system.cpu0.iq.iqSquashedInstsIssued 106 |
| system.cpu0.iq.iqSquashedInstsExamined 16685 |
| system.cpu0.iq.iqSquashedOperandsExamined 13469 |
| system.cpu0.iq.iqSquashedNonSpecRemoved 586 |
| system.cpu0.iq.issued_per_cycle::samples 222303 |
| system.cpu0.iq.issued_per_cycle::mean 2.089225 |
| system.cpu0.iq.issued_per_cycle::stdev 1.109552 |
| system.cpu0.iq.issued_per_cycle::underflows 0 0.00% 0.00% |
| system.cpu0.iq.issued_per_cycle::0 37150 16.71% 16.71% |
| system.cpu0.iq.issued_per_cycle::1 4499 2.02% 18.74% |
| system.cpu0.iq.issued_per_cycle::2 88751 39.92% 58.66% |
| system.cpu0.iq.issued_per_cycle::3 88374 39.75% 98.41% |
| system.cpu0.iq.issued_per_cycle::4 1681 0.76% 99.17% |
| system.cpu0.iq.issued_per_cycle::5 953 0.43% 99.60% |
| system.cpu0.iq.issued_per_cycle::6 547 0.25% 99.84% |
| system.cpu0.iq.issued_per_cycle::7 237 0.11% 99.95% |
| system.cpu0.iq.issued_per_cycle::8 111 0.05% 100.00% |
| system.cpu0.iq.issued_per_cycle::overflows 0 0.00% 100.00% |
| system.cpu0.iq.issued_per_cycle::min_value 0 |
| system.cpu0.iq.issued_per_cycle::max_value 8 |
| system.cpu0.iq.issued_per_cycle::total 222303 |
| system.cpu0.iq.fu_full::No_OpClass 0 0.00% 0.00% |
| system.cpu0.iq.fu_full::IntAlu 131 39.34% 39.34% |
| system.cpu0.iq.fu_full::IntMult 0 0.00% 39.34% |
| system.cpu0.iq.fu_full::IntDiv 0 0.00% 39.34% |
| system.cpu0.iq.fu_full::FloatAdd 0 0.00% 39.34% |
| system.cpu0.iq.fu_full::FloatCmp 0 0.00% 39.34% |
| system.cpu0.iq.fu_full::FloatCvt 0 0.00% 39.34% |
| system.cpu0.iq.fu_full::FloatMult 0 0.00% 39.34% |
| system.cpu0.iq.fu_full::FloatMultAcc 0 0.00% 39.34% |
| system.cpu0.iq.fu_full::FloatDiv 0 0.00% 39.34% |
| system.cpu0.iq.fu_full::FloatMisc 0 0.00% 39.34% |
| system.cpu0.iq.fu_full::FloatSqrt 0 0.00% 39.34% |
| system.cpu0.iq.fu_full::SimdAdd 0 0.00% 39.34% |
| system.cpu0.iq.fu_full::SimdAddAcc 0 0.00% 39.34% |
| system.cpu0.iq.fu_full::SimdAlu 0 0.00% 39.34% |
| system.cpu0.iq.fu_full::SimdCmp 0 0.00% 39.34% |
| system.cpu0.iq.fu_full::SimdCvt 0 0.00% 39.34% |
| system.cpu0.iq.fu_full::SimdMisc 0 0.00% 39.34% |
| system.cpu0.iq.fu_full::SimdMult 0 0.00% 39.34% |
| system.cpu0.iq.fu_full::SimdMultAcc 0 0.00% 39.34% |
| system.cpu0.iq.fu_full::SimdShift 0 0.00% 39.34% |
| system.cpu0.iq.fu_full::SimdShiftAcc 0 0.00% 39.34% |
| system.cpu0.iq.fu_full::SimdSqrt 0 0.00% 39.34% |
| system.cpu0.iq.fu_full::SimdFloatAdd 0 0.00% 39.34% |
| system.cpu0.iq.fu_full::SimdFloatAlu 0 0.00% 39.34% |
| system.cpu0.iq.fu_full::SimdFloatCmp 0 0.00% 39.34% |
| system.cpu0.iq.fu_full::SimdFloatCvt 0 0.00% 39.34% |
| system.cpu0.iq.fu_full::SimdFloatDiv 0 0.00% 39.34% |
| system.cpu0.iq.fu_full::SimdFloatMisc 0 0.00% 39.34% |
| system.cpu0.iq.fu_full::SimdFloatMult 0 0.00% 39.34% |
| system.cpu0.iq.fu_full::SimdFloatMultAcc 0 0.00% 39.34% |
| system.cpu0.iq.fu_full::SimdFloatSqrt 0 0.00% 39.34% |
| system.cpu0.iq.fu_full::MemRead 78 23.42% 62.76% |
| system.cpu0.iq.fu_full::MemWrite 124 37.24% 100.00% |
| system.cpu0.iq.fu_full::FloatMemRead 0 0.00% 100.00% |
| system.cpu0.iq.fu_full::FloatMemWrite 0 0.00% 100.00% |
| system.cpu0.iq.fu_full::IprAccess 0 0.00% 100.00% |
| system.cpu0.iq.fu_full::InstPrefetch 0 0.00% 100.00% |
| system.cpu0.iq.FU_type_0::No_OpClass 0 0.00% 0.00% |
| system.cpu0.iq.FU_type_0::IntAlu 196072 42.22% 42.22% |
| system.cpu0.iq.FU_type_0::IntMult 0 0.00% 42.22% |
| system.cpu0.iq.FU_type_0::IntDiv 0 0.00% 42.22% |
| system.cpu0.iq.FU_type_0::FloatAdd 0 0.00% 42.22% |
| system.cpu0.iq.FU_type_0::FloatCmp 0 0.00% 42.22% |
| system.cpu0.iq.FU_type_0::FloatCvt 0 0.00% 42.22% |
| system.cpu0.iq.FU_type_0::FloatMult 0 0.00% 42.22% |
| system.cpu0.iq.FU_type_0::FloatMultAcc 0 0.00% 42.22% |
| system.cpu0.iq.FU_type_0::FloatDiv 0 0.00% 42.22% |
| system.cpu0.iq.FU_type_0::FloatMisc 0 0.00% 42.22% |
| system.cpu0.iq.FU_type_0::FloatSqrt 0 0.00% 42.22% |
| system.cpu0.iq.FU_type_0::SimdAdd 0 0.00% 42.22% |
| system.cpu0.iq.FU_type_0::SimdAddAcc 0 0.00% 42.22% |
| system.cpu0.iq.FU_type_0::SimdAlu 0 0.00% 42.22% |
| system.cpu0.iq.FU_type_0::SimdCmp 0 0.00% 42.22% |
| system.cpu0.iq.FU_type_0::SimdCvt 0 0.00% 42.22% |
| system.cpu0.iq.FU_type_0::SimdMisc 0 0.00% 42.22% |
| system.cpu0.iq.FU_type_0::SimdMult 0 0.00% 42.22% |
| system.cpu0.iq.FU_type_0::SimdMultAcc 0 0.00% 42.22% |
| system.cpu0.iq.FU_type_0::SimdShift 0 0.00% 42.22% |
| system.cpu0.iq.FU_type_0::SimdShiftAcc 0 0.00% 42.22% |
| system.cpu0.iq.FU_type_0::SimdSqrt 0 0.00% 42.22% |
| system.cpu0.iq.FU_type_0::SimdFloatAdd 0 0.00% 42.22% |
| system.cpu0.iq.FU_type_0::SimdFloatAlu 0 0.00% 42.22% |
| system.cpu0.iq.FU_type_0::SimdFloatCmp 0 0.00% 42.22% |
| system.cpu0.iq.FU_type_0::SimdFloatCvt 0 0.00% 42.22% |
| system.cpu0.iq.FU_type_0::SimdFloatDiv 0 0.00% 42.22% |
| system.cpu0.iq.FU_type_0::SimdFloatMisc 0 0.00% 42.22% |
| system.cpu0.iq.FU_type_0::SimdFloatMult 0 0.00% 42.22% |
| system.cpu0.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 42.22% |
| system.cpu0.iq.FU_type_0::SimdFloatSqrt 0 0.00% 42.22% |
| system.cpu0.iq.FU_type_0::MemRead 178607 38.46% 80.67% |
| system.cpu0.iq.FU_type_0::MemWrite 89762 19.33% 100.00% |
| system.cpu0.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% |
| system.cpu0.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% |
| system.cpu0.iq.FU_type_0::IprAccess 0 0.00% 100.00% |
| system.cpu0.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% |
| system.cpu0.iq.FU_type_0::total 464441 |
| system.cpu0.iq.rate 1.835380 |
| system.cpu0.iq.fu_busy_cnt 333 |
| system.cpu0.iq.fu_busy_rate 0.000717 |
| system.cpu0.iq.int_inst_queue_reads 1151624 |
| system.cpu0.iq.int_inst_queue_writes 486378 |
| system.cpu0.iq.int_inst_queue_wakeup_accesses 461879 |
| system.cpu0.iq.fp_inst_queue_reads 0 |
| system.cpu0.iq.fp_inst_queue_writes 0 |
| system.cpu0.iq.fp_inst_queue_wakeup_accesses 0 |
| system.cpu0.iq.int_alu_accesses 464774 |
| system.cpu0.iq.fp_alu_accesses 0 |
| system.cpu0.iew.lsq.thread0.forwLoads 86836 |
| system.cpu0.iew.lsq.thread0.invAddrLoads 0 |
| system.cpu0.iew.lsq.thread0.squashedLoads 3039 |
| system.cpu0.iew.lsq.thread0.ignoredResponses 10 |
| system.cpu0.iew.lsq.thread0.memOrderViolation 54 |
| system.cpu0.iew.lsq.thread0.squashedStores 1948 |
| system.cpu0.iew.lsq.thread0.invAddrSwpfs 0 |
| system.cpu0.iew.lsq.thread0.blockedLoads 0 |
| system.cpu0.iew.lsq.thread0.rescheduledLoads 0 |
| system.cpu0.iew.lsq.thread0.cacheBlocked 12 |
| system.cpu0.iew.iewIdleCycles 0 |
| system.cpu0.iew.iewSquashCycles 1743 |
| system.cpu0.iew.iewBlockCycles 1896 |
| system.cpu0.iew.iewUnblockCycles 25 |
| system.cpu0.iew.iewDispatchedInsts 557675 |
| system.cpu0.iew.iewDispSquashedInsts 154 |
| system.cpu0.iew.iewDispLoadInsts 179238 |
| system.cpu0.iew.iewDispStoreInsts 90554 |
| system.cpu0.iew.iewDispNonSpecInsts 1020 |
| system.cpu0.iew.iewIQFullEvents 25 |
| system.cpu0.iew.iewLSQFullEvents 0 |
| system.cpu0.iew.memOrderViolationEvents 54 |
| system.cpu0.iew.predictedTakenIncorrect 223 |
| system.cpu0.iew.predictedNotTakenIncorrect 1713 |
| system.cpu0.iew.branchMispredicts 1936 |
| system.cpu0.iew.iewExecutedInsts 462987 |
| system.cpu0.iew.iewExecLoadInsts 178230 |
| system.cpu0.iew.iewExecSquashedInsts 1454 |
| system.cpu0.iew.exec_swp 0 |
| system.cpu0.iew.exec_nop 88034 |
| system.cpu0.iew.exec_refs 267793 |
| system.cpu0.iew.exec_branches 91939 |
| system.cpu0.iew.exec_stores 89563 |
| system.cpu0.iew.exec_rate 1.829634 |
| system.cpu0.iew.wb_sent 462340 |
| system.cpu0.iew.wb_count 461879 |
| system.cpu0.iew.wb_producers 273734 |
| system.cpu0.iew.wb_consumers 277281 |
| system.cpu0.iew.wb_rate 1.825255 |
| system.cpu0.iew.wb_fanout 0.987208 |
| system.cpu0.commit.commitSquashedInsts 17412 |
| system.cpu0.commit.commitNonSpecStalls 559 |
| system.cpu0.commit.branchMispredicts 1594 |
| system.cpu0.commit.committed_per_cycle::samples 218890 |
| system.cpu0.commit.committed_per_cycle::mean 2.467815 |
| system.cpu0.commit.committed_per_cycle::stdev 2.142481 |
| system.cpu0.commit.committed_per_cycle::underflows 0 0.00% 0.00% |
| system.cpu0.commit.committed_per_cycle::0 37135 16.97% 16.97% |
| system.cpu0.commit.committed_per_cycle::1 90773 41.47% 58.43% |
| system.cpu0.commit.committed_per_cycle::2 2099 0.96% 59.39% |
| system.cpu0.commit.committed_per_cycle::3 598 0.27% 59.67% |
| system.cpu0.commit.committed_per_cycle::4 457 0.21% 59.88% |
| system.cpu0.commit.committed_per_cycle::5 86592 39.56% 99.44% |
| system.cpu0.commit.committed_per_cycle::6 481 0.22% 99.66% |
| system.cpu0.commit.committed_per_cycle::7 299 0.14% 99.79% |
| system.cpu0.commit.committed_per_cycle::8 456 0.21% 100.00% |
| system.cpu0.commit.committed_per_cycle::overflows 0 0.00% 100.00% |
| system.cpu0.commit.committed_per_cycle::min_value 0 |
| system.cpu0.commit.committed_per_cycle::max_value 8 |
| system.cpu0.commit.committed_per_cycle::total 218890 |
| system.cpu0.commit.committedInsts 540180 |
| system.cpu0.commit.committedOps 540180 |
| system.cpu0.commit.swp_count 0 |
| system.cpu0.commit.refs 264805 |
| system.cpu0.commit.loads 176199 |
| system.cpu0.commit.membars 84 |
| system.cpu0.commit.branches 90493 |
| system.cpu0.commit.fp_insts 0 |
| system.cpu0.commit.int_insts 363550 |
| system.cpu0.commit.function_calls 223 |
| system.cpu0.commit.op_class_0::No_OpClass 87225 16.15% 16.15% |
| system.cpu0.commit.op_class_0::IntAlu 188066 34.82% 50.96% |
| system.cpu0.commit.op_class_0::IntMult 0 0.00% 50.96% |
| system.cpu0.commit.op_class_0::IntDiv 0 0.00% 50.96% |
| system.cpu0.commit.op_class_0::FloatAdd 0 0.00% 50.96% |
| system.cpu0.commit.op_class_0::FloatCmp 0 0.00% 50.96% |
| system.cpu0.commit.op_class_0::FloatCvt 0 0.00% 50.96% |
| system.cpu0.commit.op_class_0::FloatMult 0 0.00% 50.96% |
| system.cpu0.commit.op_class_0::FloatMultAcc 0 0.00% 50.96% |
| system.cpu0.commit.op_class_0::FloatDiv 0 0.00% 50.96% |
| system.cpu0.commit.op_class_0::FloatMisc 0 0.00% 50.96% |
| system.cpu0.commit.op_class_0::FloatSqrt 0 0.00% 50.96% |
| system.cpu0.commit.op_class_0::SimdAdd 0 0.00% 50.96% |
| system.cpu0.commit.op_class_0::SimdAddAcc 0 0.00% 50.96% |
| system.cpu0.commit.op_class_0::SimdAlu 0 0.00% 50.96% |
| system.cpu0.commit.op_class_0::SimdCmp 0 0.00% 50.96% |
| system.cpu0.commit.op_class_0::SimdCvt 0 0.00% 50.96% |
| system.cpu0.commit.op_class_0::SimdMisc 0 0.00% 50.96% |
| system.cpu0.commit.op_class_0::SimdMult 0 0.00% 50.96% |
| system.cpu0.commit.op_class_0::SimdMultAcc 0 0.00% 50.96% |
| system.cpu0.commit.op_class_0::SimdShift 0 0.00% 50.96% |
| system.cpu0.commit.op_class_0::SimdShiftAcc 0 0.00% 50.96% |
| system.cpu0.commit.op_class_0::SimdSqrt 0 0.00% 50.96% |
| system.cpu0.commit.op_class_0::SimdFloatAdd 0 0.00% 50.96% |
| system.cpu0.commit.op_class_0::SimdFloatAlu 0 0.00% 50.96% |
| system.cpu0.commit.op_class_0::SimdFloatCmp 0 0.00% 50.96% |
| system.cpu0.commit.op_class_0::SimdFloatCvt 0 0.00% 50.96% |
| system.cpu0.commit.op_class_0::SimdFloatDiv 0 0.00% 50.96% |
| system.cpu0.commit.op_class_0::SimdFloatMisc 0 0.00% 50.96% |
| system.cpu0.commit.op_class_0::SimdFloatMult 0 0.00% 50.96% |
| system.cpu0.commit.op_class_0::SimdFloatMultAcc 0 0.00% 50.96% |
| system.cpu0.commit.op_class_0::SimdFloatSqrt 0 0.00% 50.96% |
| system.cpu0.commit.op_class_0::MemRead 176283 32.63% 83.60% |
| system.cpu0.commit.op_class_0::MemWrite 88606 16.40% 100.00% |
| system.cpu0.commit.op_class_0::FloatMemRead 0 0.00% 100.00% |
| system.cpu0.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% |
| system.cpu0.commit.op_class_0::IprAccess 0 0.00% 100.00% |
| system.cpu0.commit.op_class_0::InstPrefetch 0 0.00% 100.00% |
| system.cpu0.commit.op_class_0::total 540180 |
| system.cpu0.commit.bw_lim_events 456 |
| system.cpu0.rob.rob_reads 774865 |
| system.cpu0.rob.rob_writes 1118643 |
| system.cpu0.timesIdled 329 |
| system.cpu0.idleCycles 30746 |
| system.cpu0.committedInsts 452871 |
| system.cpu0.committedOps 452871 |
| system.cpu0.cpi 0.558766 |
| system.cpu0.cpi_total 0.558766 |
| system.cpu0.ipc 1.789657 |
| system.cpu0.ipc_total 1.789657 |
| system.cpu0.int_regfile_reads 827809 |
| system.cpu0.int_regfile_writes 373052 |
| system.cpu0.fp_regfile_reads 192 |
| system.cpu0.misc_regfile_reads 269916 |
| system.cpu0.misc_regfile_writes 564 |
| system.cpu0.dcache.tags.pwrStateResidencyTicks::UNDEFINED 126524000 |
| system.cpu0.dcache.tags.replacements 2 |
| system.cpu0.dcache.tags.tagsinuse 142.437972 |
| system.cpu0.dcache.tags.total_refs 178652 |
| system.cpu0.dcache.tags.sampled_refs 171 |
| system.cpu0.dcache.tags.avg_refs 1044.748538 |
| system.cpu0.dcache.tags.warmup_cycle 0 |
| system.cpu0.dcache.tags.occ_blocks::cpu0.data 142.437972 |
| system.cpu0.dcache.tags.occ_percent::cpu0.data 0.278199 |
| system.cpu0.dcache.tags.occ_percent::total 0.278199 |
| system.cpu0.dcache.tags.occ_task_id_blocks::1024 169 |
| system.cpu0.dcache.tags.age_task_id_blocks_1024::0 18 |
| system.cpu0.dcache.tags.age_task_id_blocks_1024::1 8 |
| system.cpu0.dcache.tags.age_task_id_blocks_1024::2 143 |
| system.cpu0.dcache.tags.occ_task_id_percent::1024 0.330078 |
| system.cpu0.dcache.tags.tag_accesses 719933 |
| system.cpu0.dcache.tags.data_accesses 719933 |
| system.cpu0.dcache.pwrStateResidencyTicks::UNDEFINED 126524000 |
| system.cpu0.dcache.ReadReq_hits::cpu0.data 90725 |
| system.cpu0.dcache.ReadReq_hits::total 90725 |
| system.cpu0.dcache.WriteReq_hits::cpu0.data 88017 |
| system.cpu0.dcache.WriteReq_hits::total 88017 |
| system.cpu0.dcache.SwapReq_hits::cpu0.data 17 |
| system.cpu0.dcache.SwapReq_hits::total 17 |
| system.cpu0.dcache.demand_hits::cpu0.data 178742 |
| system.cpu0.dcache.demand_hits::total 178742 |
| system.cpu0.dcache.overall_hits::cpu0.data 178742 |
| system.cpu0.dcache.overall_hits::total 178742 |
| system.cpu0.dcache.ReadReq_misses::cpu0.data 571 |
| system.cpu0.dcache.ReadReq_misses::total 571 |
| system.cpu0.dcache.WriteReq_misses::cpu0.data 547 |
| system.cpu0.dcache.WriteReq_misses::total 547 |
| system.cpu0.dcache.SwapReq_misses::cpu0.data 25 |
| system.cpu0.dcache.SwapReq_misses::total 25 |
| system.cpu0.dcache.demand_misses::cpu0.data 1118 |
| system.cpu0.dcache.demand_misses::total 1118 |
| system.cpu0.dcache.overall_misses::cpu0.data 1118 |
| system.cpu0.dcache.overall_misses::total 1118 |
| system.cpu0.dcache.ReadReq_miss_latency::cpu0.data 15765500 |
| system.cpu0.dcache.ReadReq_miss_latency::total 15765500 |
| system.cpu0.dcache.WriteReq_miss_latency::cpu0.data 35483989 |
| system.cpu0.dcache.WriteReq_miss_latency::total 35483989 |
| system.cpu0.dcache.SwapReq_miss_latency::cpu0.data 519500 |
| system.cpu0.dcache.SwapReq_miss_latency::total 519500 |
| system.cpu0.dcache.demand_miss_latency::cpu0.data 51249489 |
| system.cpu0.dcache.demand_miss_latency::total 51249489 |
| system.cpu0.dcache.overall_miss_latency::cpu0.data 51249489 |
| system.cpu0.dcache.overall_miss_latency::total 51249489 |
| system.cpu0.dcache.ReadReq_accesses::cpu0.data 91296 |
| system.cpu0.dcache.ReadReq_accesses::total 91296 |
| system.cpu0.dcache.WriteReq_accesses::cpu0.data 88564 |
| system.cpu0.dcache.WriteReq_accesses::total 88564 |
| system.cpu0.dcache.SwapReq_accesses::cpu0.data 42 |
| system.cpu0.dcache.SwapReq_accesses::total 42 |
| system.cpu0.dcache.demand_accesses::cpu0.data 179860 |
| system.cpu0.dcache.demand_accesses::total 179860 |
| system.cpu0.dcache.overall_accesses::cpu0.data 179860 |
| system.cpu0.dcache.overall_accesses::total 179860 |
| system.cpu0.dcache.ReadReq_miss_rate::cpu0.data 0.006254 |
| system.cpu0.dcache.ReadReq_miss_rate::total 0.006254 |
| system.cpu0.dcache.WriteReq_miss_rate::cpu0.data 0.006176 |
| system.cpu0.dcache.WriteReq_miss_rate::total 0.006176 |
| system.cpu0.dcache.SwapReq_miss_rate::cpu0.data 0.595238 |
| system.cpu0.dcache.SwapReq_miss_rate::total 0.595238 |
| system.cpu0.dcache.demand_miss_rate::cpu0.data 0.006216 |
| system.cpu0.dcache.demand_miss_rate::total 0.006216 |
| system.cpu0.dcache.overall_miss_rate::cpu0.data 0.006216 |
| system.cpu0.dcache.overall_miss_rate::total 0.006216 |
| system.cpu0.dcache.ReadReq_avg_miss_latency::cpu0.data 27610.332750 |
| system.cpu0.dcache.ReadReq_avg_miss_latency::total 27610.332750 |
| system.cpu0.dcache.WriteReq_avg_miss_latency::cpu0.data 64870.180987 |
| system.cpu0.dcache.WriteReq_avg_miss_latency::total 64870.180987 |
| system.cpu0.dcache.SwapReq_avg_miss_latency::cpu0.data 20780 |
| system.cpu0.dcache.SwapReq_avg_miss_latency::total 20780 |
| system.cpu0.dcache.demand_avg_miss_latency::cpu0.data 45840.330054 |
| system.cpu0.dcache.demand_avg_miss_latency::total 45840.330054 |
| system.cpu0.dcache.overall_avg_miss_latency::cpu0.data 45840.330054 |
| system.cpu0.dcache.overall_avg_miss_latency::total 45840.330054 |
| system.cpu0.dcache.blocked_cycles::no_mshrs 885 |
| system.cpu0.dcache.blocked_cycles::no_targets 0 |
| system.cpu0.dcache.blocked::no_mshrs 21 |
| system.cpu0.dcache.blocked::no_targets 0 |
| system.cpu0.dcache.avg_blocked_cycles::no_mshrs 42.142857 |
| system.cpu0.dcache.avg_blocked_cycles::no_targets nan |
| system.cpu0.dcache.writebacks::writebacks 1 |
| system.cpu0.dcache.writebacks::total 1 |
| system.cpu0.dcache.ReadReq_mshr_hits::cpu0.data 371 |
| system.cpu0.dcache.ReadReq_mshr_hits::total 371 |
| system.cpu0.dcache.WriteReq_mshr_hits::cpu0.data 380 |
| system.cpu0.dcache.WriteReq_mshr_hits::total 380 |
| system.cpu0.dcache.demand_mshr_hits::cpu0.data 751 |
| system.cpu0.dcache.demand_mshr_hits::total 751 |
| system.cpu0.dcache.overall_mshr_hits::cpu0.data 751 |
| system.cpu0.dcache.overall_mshr_hits::total 751 |
| system.cpu0.dcache.ReadReq_mshr_misses::cpu0.data 200 |
| system.cpu0.dcache.ReadReq_mshr_misses::total 200 |
| system.cpu0.dcache.WriteReq_mshr_misses::cpu0.data 167 |
| system.cpu0.dcache.WriteReq_mshr_misses::total 167 |
| system.cpu0.dcache.SwapReq_mshr_misses::cpu0.data 25 |
| system.cpu0.dcache.SwapReq_mshr_misses::total 25 |
| system.cpu0.dcache.demand_mshr_misses::cpu0.data 367 |
| system.cpu0.dcache.demand_mshr_misses::total 367 |
| system.cpu0.dcache.overall_mshr_misses::cpu0.data 367 |
| system.cpu0.dcache.overall_mshr_misses::total 367 |
| system.cpu0.dcache.ReadReq_mshr_miss_latency::cpu0.data 7360500 |
| system.cpu0.dcache.ReadReq_mshr_miss_latency::total 7360500 |
| system.cpu0.dcache.WriteReq_mshr_miss_latency::cpu0.data 8143000 |
| system.cpu0.dcache.WriteReq_mshr_miss_latency::total 8143000 |
| system.cpu0.dcache.SwapReq_mshr_miss_latency::cpu0.data 494500 |
| system.cpu0.dcache.SwapReq_mshr_miss_latency::total 494500 |
| system.cpu0.dcache.demand_mshr_miss_latency::cpu0.data 15503500 |
| system.cpu0.dcache.demand_mshr_miss_latency::total 15503500 |
| system.cpu0.dcache.overall_mshr_miss_latency::cpu0.data 15503500 |
| system.cpu0.dcache.overall_mshr_miss_latency::total 15503500 |
| system.cpu0.dcache.ReadReq_mshr_miss_rate::cpu0.data 0.002191 |
| system.cpu0.dcache.ReadReq_mshr_miss_rate::total 0.002191 |
| system.cpu0.dcache.WriteReq_mshr_miss_rate::cpu0.data 0.001886 |
| system.cpu0.dcache.WriteReq_mshr_miss_rate::total 0.001886 |
| system.cpu0.dcache.SwapReq_mshr_miss_rate::cpu0.data 0.595238 |
| system.cpu0.dcache.SwapReq_mshr_miss_rate::total 0.595238 |
| system.cpu0.dcache.demand_mshr_miss_rate::cpu0.data 0.002040 |
| system.cpu0.dcache.demand_mshr_miss_rate::total 0.002040 |
| system.cpu0.dcache.overall_mshr_miss_rate::cpu0.data 0.002040 |
| system.cpu0.dcache.overall_mshr_miss_rate::total 0.002040 |
| system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::cpu0.data 36802.500000 |
| system.cpu0.dcache.ReadReq_avg_mshr_miss_latency::total 36802.500000 |
| system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::cpu0.data 48760.479042 |
| system.cpu0.dcache.WriteReq_avg_mshr_miss_latency::total 48760.479042 |
| system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::cpu0.data 19780 |
| system.cpu0.dcache.SwapReq_avg_mshr_miss_latency::total 19780 |
| system.cpu0.dcache.demand_avg_mshr_miss_latency::cpu0.data 42243.869210 |
| system.cpu0.dcache.demand_avg_mshr_miss_latency::total 42243.869210 |
| system.cpu0.dcache.overall_avg_mshr_miss_latency::cpu0.data 42243.869210 |
| system.cpu0.dcache.overall_avg_mshr_miss_latency::total 42243.869210 |
| system.cpu0.icache.tags.pwrStateResidencyTicks::UNDEFINED 126524000 |
| system.cpu0.icache.tags.replacements 389 |
| system.cpu0.icache.tags.tagsinuse 247.660025 |
| system.cpu0.icache.tags.total_refs 7239 |
| system.cpu0.icache.tags.sampled_refs 689 |
| system.cpu0.icache.tags.avg_refs 10.506531 |
| system.cpu0.icache.tags.warmup_cycle 0 |
| system.cpu0.icache.tags.occ_blocks::cpu0.inst 247.660025 |
| system.cpu0.icache.tags.occ_percent::cpu0.inst 0.483711 |
| system.cpu0.icache.tags.occ_percent::total 0.483711 |
| system.cpu0.icache.tags.occ_task_id_blocks::1024 300 |
| system.cpu0.icache.tags.age_task_id_blocks_1024::0 67 |
| system.cpu0.icache.tags.age_task_id_blocks_1024::1 40 |
| system.cpu0.icache.tags.age_task_id_blocks_1024::2 193 |
| system.cpu0.icache.tags.occ_task_id_percent::1024 0.585938 |
| system.cpu0.icache.tags.tag_accesses 8839 |
| system.cpu0.icache.tags.data_accesses 8839 |
| system.cpu0.icache.pwrStateResidencyTicks::UNDEFINED 126524000 |
| system.cpu0.icache.ReadReq_hits::cpu0.inst 7239 |
| system.cpu0.icache.ReadReq_hits::total 7239 |
| system.cpu0.icache.demand_hits::cpu0.inst 7239 |
| system.cpu0.icache.demand_hits::total 7239 |
| system.cpu0.icache.overall_hits::cpu0.inst 7239 |
| system.cpu0.icache.overall_hits::total 7239 |
| system.cpu0.icache.ReadReq_misses::cpu0.inst 911 |
| system.cpu0.icache.ReadReq_misses::total 911 |
| system.cpu0.icache.demand_misses::cpu0.inst 911 |
| system.cpu0.icache.demand_misses::total 911 |
| system.cpu0.icache.overall_misses::cpu0.inst 911 |
| system.cpu0.icache.overall_misses::total 911 |
| system.cpu0.icache.ReadReq_miss_latency::cpu0.inst 46831000 |
| system.cpu0.icache.ReadReq_miss_latency::total 46831000 |
| system.cpu0.icache.demand_miss_latency::cpu0.inst 46831000 |
| system.cpu0.icache.demand_miss_latency::total 46831000 |
| system.cpu0.icache.overall_miss_latency::cpu0.inst 46831000 |
| system.cpu0.icache.overall_miss_latency::total 46831000 |
| system.cpu0.icache.ReadReq_accesses::cpu0.inst 8150 |
| system.cpu0.icache.ReadReq_accesses::total 8150 |
| system.cpu0.icache.demand_accesses::cpu0.inst 8150 |
| system.cpu0.icache.demand_accesses::total 8150 |
| system.cpu0.icache.overall_accesses::cpu0.inst 8150 |
| system.cpu0.icache.overall_accesses::total 8150 |
| system.cpu0.icache.ReadReq_miss_rate::cpu0.inst 0.111779 |
| system.cpu0.icache.ReadReq_miss_rate::total 0.111779 |
| system.cpu0.icache.demand_miss_rate::cpu0.inst 0.111779 |
| system.cpu0.icache.demand_miss_rate::total 0.111779 |
| system.cpu0.icache.overall_miss_rate::cpu0.inst 0.111779 |
| system.cpu0.icache.overall_miss_rate::total 0.111779 |
| system.cpu0.icache.ReadReq_avg_miss_latency::cpu0.inst 51406.147091 |
| system.cpu0.icache.ReadReq_avg_miss_latency::total 51406.147091 |
| system.cpu0.icache.demand_avg_miss_latency::cpu0.inst 51406.147091 |
| system.cpu0.icache.demand_avg_miss_latency::total 51406.147091 |
| system.cpu0.icache.overall_avg_miss_latency::cpu0.inst 51406.147091 |
| system.cpu0.icache.overall_avg_miss_latency::total 51406.147091 |
| system.cpu0.icache.blocked_cycles::no_mshrs 84 |
| system.cpu0.icache.blocked_cycles::no_targets 0 |
| system.cpu0.icache.blocked::no_mshrs 3 |
| system.cpu0.icache.blocked::no_targets 0 |
| system.cpu0.icache.avg_blocked_cycles::no_mshrs 28 |
| system.cpu0.icache.avg_blocked_cycles::no_targets nan |
| system.cpu0.icache.writebacks::writebacks 389 |
| system.cpu0.icache.writebacks::total 389 |
| system.cpu0.icache.ReadReq_mshr_hits::cpu0.inst 221 |
| system.cpu0.icache.ReadReq_mshr_hits::total 221 |
| system.cpu0.icache.demand_mshr_hits::cpu0.inst 221 |
| system.cpu0.icache.demand_mshr_hits::total 221 |
| system.cpu0.icache.overall_mshr_hits::cpu0.inst 221 |
| system.cpu0.icache.overall_mshr_hits::total 221 |
| system.cpu0.icache.ReadReq_mshr_misses::cpu0.inst 690 |
| system.cpu0.icache.ReadReq_mshr_misses::total 690 |
| system.cpu0.icache.demand_mshr_misses::cpu0.inst 690 |
| system.cpu0.icache.demand_mshr_misses::total 690 |
| system.cpu0.icache.overall_mshr_misses::cpu0.inst 690 |
| system.cpu0.icache.overall_mshr_misses::total 690 |
| system.cpu0.icache.ReadReq_mshr_miss_latency::cpu0.inst 35682500 |
| system.cpu0.icache.ReadReq_mshr_miss_latency::total 35682500 |
| system.cpu0.icache.demand_mshr_miss_latency::cpu0.inst 35682500 |
| system.cpu0.icache.demand_mshr_miss_latency::total 35682500 |
| system.cpu0.icache.overall_mshr_miss_latency::cpu0.inst 35682500 |
| system.cpu0.icache.overall_mshr_miss_latency::total 35682500 |
| system.cpu0.icache.ReadReq_mshr_miss_rate::cpu0.inst 0.084663 |
| system.cpu0.icache.ReadReq_mshr_miss_rate::total 0.084663 |
| system.cpu0.icache.demand_mshr_miss_rate::cpu0.inst 0.084663 |
| system.cpu0.icache.demand_mshr_miss_rate::total 0.084663 |
| system.cpu0.icache.overall_mshr_miss_rate::cpu0.inst 0.084663 |
| system.cpu0.icache.overall_mshr_miss_rate::total 0.084663 |
| system.cpu0.icache.ReadReq_avg_mshr_miss_latency::cpu0.inst 51713.768116 |
| system.cpu0.icache.ReadReq_avg_mshr_miss_latency::total 51713.768116 |
| system.cpu0.icache.demand_avg_mshr_miss_latency::cpu0.inst 51713.768116 |
| system.cpu0.icache.demand_avg_mshr_miss_latency::total 51713.768116 |
| system.cpu0.icache.overall_avg_mshr_miss_latency::cpu0.inst 51713.768116 |
| system.cpu0.icache.overall_avg_mshr_miss_latency::total 51713.768116 |
| system.cpu1.branchPred.lookups 63294 |
| system.cpu1.branchPred.condPredicted 55557 |
| system.cpu1.branchPred.condIncorrect 2283 |
| system.cpu1.branchPred.BTBLookups 55348 |
| system.cpu1.branchPred.BTBHits 0 |
| system.cpu1.branchPred.BTBCorrect 0 |
| system.cpu1.branchPred.BTBHitPct 0.000000 |
| system.cpu1.branchPred.usedRAS 1956 |
| system.cpu1.branchPred.RASInCorrect 231 |
| system.cpu1.branchPred.indirectLookups 55348 |
| system.cpu1.branchPred.indirectHits 45091 |
| system.cpu1.branchPred.indirectMisses 10257 |
| system.cpu1.branchPredindirectMispredicted 1210 |
| system.cpu1.pwrStateResidencyTicks::ON 126524000 |
| system.cpu1.numCycles 193951 |
| system.cpu1.numWorkItemsStarted 0 |
| system.cpu1.numWorkItemsCompleted 0 |
| system.cpu1.fetch.icacheStallCycles 40389 |
| system.cpu1.fetch.Insts 341951 |
| system.cpu1.fetch.Branches 63294 |
| system.cpu1.fetch.predictedBranches 47047 |
| system.cpu1.fetch.Cycles 142781 |
| system.cpu1.fetch.SquashCycles 4723 |
| system.cpu1.fetch.MiscStallCycles 6 |
| system.cpu1.fetch.NoActiveThreadStallCycles 10 |
| system.cpu1.fetch.PendingTrapStallCycles 1381 |
| system.cpu1.fetch.IcacheWaitRetryStallCycles 38 |
| system.cpu1.fetch.CacheLines 28562 |
| system.cpu1.fetch.IcacheSquashes 991 |
| system.cpu1.fetch.rateDist::samples 186966 |
| system.cpu1.fetch.rateDist::mean 1.828948 |
| system.cpu1.fetch.rateDist::stdev 2.328595 |
| system.cpu1.fetch.rateDist::underflows 0 0.00% 0.00% |
| system.cpu1.fetch.rateDist::0 72547 38.80% 38.80% |
| system.cpu1.fetch.rateDist::1 56594 30.27% 69.07% |
| system.cpu1.fetch.rateDist::2 8597 4.60% 73.67% |
| system.cpu1.fetch.rateDist::3 3330 1.78% 75.45% |
| system.cpu1.fetch.rateDist::4 695 0.37% 75.82% |
| system.cpu1.fetch.rateDist::5 34236 18.31% 94.13% |
| system.cpu1.fetch.rateDist::6 1093 0.58% 94.72% |
| system.cpu1.fetch.rateDist::7 1337 0.72% 95.43% |
| system.cpu1.fetch.rateDist::8 8537 4.57% 100.00% |
| system.cpu1.fetch.rateDist::overflows 0 0.00% 100.00% |
| system.cpu1.fetch.rateDist::min_value 0 |
| system.cpu1.fetch.rateDist::max_value 8 |
| system.cpu1.fetch.rateDist::total 186966 |
| system.cpu1.fetch.branchRate 0.326340 |
| system.cpu1.fetch.rate 1.763079 |
| system.cpu1.decode.IdleCycles 22891 |
| system.cpu1.decode.BlockedCycles 71776 |
| system.cpu1.decode.RunCycles 85305 |
| system.cpu1.decode.UnblockCycles 4623 |
| system.cpu1.decode.SquashCycles 2361 |
| system.cpu1.decode.DecodedInsts 310456 |
| system.cpu1.rename.SquashCycles 2361 |
| system.cpu1.rename.IdleCycles 23853 |
| system.cpu1.rename.BlockCycles 35144 |
| system.cpu1.rename.serializeStallCycles 13312 |
| system.cpu1.rename.RunCycles 86491 |
| system.cpu1.rename.UnblockCycles 25795 |
| system.cpu1.rename.RenamedInsts 304191 |
| system.cpu1.rename.IQFullEvents 22567 |
| system.cpu1.rename.LQFullEvents 13 |
| system.cpu1.rename.FullRegisterEvents 3 |
| system.cpu1.rename.RenamedOperands 212285 |
| system.cpu1.rename.RenameLookups 574883 |
| system.cpu1.rename.int_rename_lookups 448400 |
| system.cpu1.rename.fp_rename_lookups 44 |
| system.cpu1.rename.CommittedMaps 185221 |
| system.cpu1.rename.UndoneMaps 27064 |
| system.cpu1.rename.serializingInsts 1647 |
| system.cpu1.rename.tempSerializingInsts 1783 |
| system.cpu1.rename.skidInsts 31202 |
| system.cpu1.memDep0.insertedLoads 82743 |
| system.cpu1.memDep0.insertedStores 38627 |
| system.cpu1.memDep0.conflictingLoads 39639 |
| system.cpu1.memDep0.conflictingStores 32322 |
| system.cpu1.iq.iqInstsAdded 247154 |
| system.cpu1.iq.iqNonSpecInstsAdded 8855 |
| system.cpu1.iq.iqInstsIssued 248497 |
| system.cpu1.iq.iqSquashedInstsIssued 91 |
| system.cpu1.iq.iqSquashedInstsExamined 23477 |
| system.cpu1.iq.iqSquashedOperandsExamined 18537 |
| system.cpu1.iq.iqSquashedNonSpecRemoved 1202 |
| system.cpu1.iq.issued_per_cycle::samples 186966 |
| system.cpu1.iq.issued_per_cycle::mean 1.329103 |
| system.cpu1.iq.issued_per_cycle::stdev 1.385649 |
| system.cpu1.iq.issued_per_cycle::underflows 0 0.00% 0.00% |
| system.cpu1.iq.issued_per_cycle::0 77442 41.42% 41.42% |
| system.cpu1.iq.issued_per_cycle::1 28211 15.09% 56.51% |
| system.cpu1.iq.issued_per_cycle::2 37135 19.86% 76.37% |
| system.cpu1.iq.issued_per_cycle::3 36997 19.79% 96.16% |
| system.cpu1.iq.issued_per_cycle::4 3585 1.92% 98.08% |
| system.cpu1.iq.issued_per_cycle::5 1867 1.00% 99.08% |
| system.cpu1.iq.issued_per_cycle::6 1035 0.55% 99.63% |
| system.cpu1.iq.issued_per_cycle::7 412 0.22% 99.85% |
| system.cpu1.iq.issued_per_cycle::8 282 0.15% 100.00% |
| system.cpu1.iq.issued_per_cycle::overflows 0 0.00% 100.00% |
| system.cpu1.iq.issued_per_cycle::min_value 0 |
| system.cpu1.iq.issued_per_cycle::max_value 8 |
| system.cpu1.iq.issued_per_cycle::total 186966 |
| system.cpu1.iq.fu_full::No_OpClass 0 0.00% 0.00% |
| system.cpu1.iq.fu_full::IntAlu 182 38.56% 38.56% |
| system.cpu1.iq.fu_full::IntMult 0 0.00% 38.56% |
| system.cpu1.iq.fu_full::IntDiv 0 0.00% 38.56% |
| system.cpu1.iq.fu_full::FloatAdd 0 0.00% 38.56% |
| system.cpu1.iq.fu_full::FloatCmp 0 0.00% 38.56% |
| system.cpu1.iq.fu_full::FloatCvt 0 0.00% 38.56% |
| system.cpu1.iq.fu_full::FloatMult 0 0.00% 38.56% |
| system.cpu1.iq.fu_full::FloatMultAcc 0 0.00% 38.56% |
| system.cpu1.iq.fu_full::FloatDiv 0 0.00% 38.56% |
| system.cpu1.iq.fu_full::FloatMisc 0 0.00% 38.56% |
| system.cpu1.iq.fu_full::FloatSqrt 0 0.00% 38.56% |
| system.cpu1.iq.fu_full::SimdAdd 0 0.00% 38.56% |
| system.cpu1.iq.fu_full::SimdAddAcc 0 0.00% 38.56% |
| system.cpu1.iq.fu_full::SimdAlu 0 0.00% 38.56% |
| system.cpu1.iq.fu_full::SimdCmp 0 0.00% 38.56% |
| system.cpu1.iq.fu_full::SimdCvt 0 0.00% 38.56% |
| system.cpu1.iq.fu_full::SimdMisc 0 0.00% 38.56% |
| system.cpu1.iq.fu_full::SimdMult 0 0.00% 38.56% |
| system.cpu1.iq.fu_full::SimdMultAcc 0 0.00% 38.56% |
| system.cpu1.iq.fu_full::SimdShift 0 0.00% 38.56% |
| system.cpu1.iq.fu_full::SimdShiftAcc 0 0.00% 38.56% |
| system.cpu1.iq.fu_full::SimdSqrt 0 0.00% 38.56% |
| system.cpu1.iq.fu_full::SimdFloatAdd 0 0.00% 38.56% |
| system.cpu1.iq.fu_full::SimdFloatAlu 0 0.00% 38.56% |
| system.cpu1.iq.fu_full::SimdFloatCmp 0 0.00% 38.56% |
| system.cpu1.iq.fu_full::SimdFloatCvt 0 0.00% 38.56% |
| system.cpu1.iq.fu_full::SimdFloatDiv 0 0.00% 38.56% |
| system.cpu1.iq.fu_full::SimdFloatMisc 0 0.00% 38.56% |
| system.cpu1.iq.fu_full::SimdFloatMult 0 0.00% 38.56% |
| system.cpu1.iq.fu_full::SimdFloatMultAcc 0 0.00% 38.56% |
| system.cpu1.iq.fu_full::SimdFloatSqrt 0 0.00% 38.56% |
| system.cpu1.iq.fu_full::MemRead 56 11.86% 50.42% |
| system.cpu1.iq.fu_full::MemWrite 234 49.58% 100.00% |
| system.cpu1.iq.fu_full::FloatMemRead 0 0.00% 100.00% |
| system.cpu1.iq.fu_full::FloatMemWrite 0 0.00% 100.00% |
| system.cpu1.iq.fu_full::IprAccess 0 0.00% 100.00% |
| system.cpu1.iq.fu_full::InstPrefetch 0 0.00% 100.00% |
| system.cpu1.iq.FU_type_0::No_OpClass 0 0.00% 0.00% |
| system.cpu1.iq.FU_type_0::IntAlu 122183 49.17% 49.17% |
| system.cpu1.iq.FU_type_0::IntMult 0 0.00% 49.17% |
| system.cpu1.iq.FU_type_0::IntDiv 0 0.00% 49.17% |
| system.cpu1.iq.FU_type_0::FloatAdd 0 0.00% 49.17% |
| system.cpu1.iq.FU_type_0::FloatCmp 0 0.00% 49.17% |
| system.cpu1.iq.FU_type_0::FloatCvt 0 0.00% 49.17% |
| system.cpu1.iq.FU_type_0::FloatMult 0 0.00% 49.17% |
| system.cpu1.iq.FU_type_0::FloatMultAcc 0 0.00% 49.17% |
| system.cpu1.iq.FU_type_0::FloatDiv 0 0.00% 49.17% |
| system.cpu1.iq.FU_type_0::FloatMisc 0 0.00% 49.17% |
| system.cpu1.iq.FU_type_0::FloatSqrt 0 0.00% 49.17% |
| system.cpu1.iq.FU_type_0::SimdAdd 0 0.00% 49.17% |
| system.cpu1.iq.FU_type_0::SimdAddAcc 0 0.00% 49.17% |
| system.cpu1.iq.FU_type_0::SimdAlu 0 0.00% 49.17% |
| system.cpu1.iq.FU_type_0::SimdCmp 0 0.00% 49.17% |
| system.cpu1.iq.FU_type_0::SimdCvt 0 0.00% 49.17% |
| system.cpu1.iq.FU_type_0::SimdMisc 0 0.00% 49.17% |
| system.cpu1.iq.FU_type_0::SimdMult 0 0.00% 49.17% |
| system.cpu1.iq.FU_type_0::SimdMultAcc 0 0.00% 49.17% |
| system.cpu1.iq.FU_type_0::SimdShift 0 0.00% 49.17% |
| system.cpu1.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.17% |
| system.cpu1.iq.FU_type_0::SimdSqrt 0 0.00% 49.17% |
| system.cpu1.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.17% |
| system.cpu1.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.17% |
| system.cpu1.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.17% |
| system.cpu1.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.17% |
| system.cpu1.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.17% |
| system.cpu1.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.17% |
| system.cpu1.iq.FU_type_0::SimdFloatMult 0 0.00% 49.17% |
| system.cpu1.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.17% |
| system.cpu1.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.17% |
| system.cpu1.iq.FU_type_0::MemRead 88669 35.68% 84.85% |
| system.cpu1.iq.FU_type_0::MemWrite 37645 15.15% 100.00% |
| system.cpu1.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% |
| system.cpu1.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% |
| system.cpu1.iq.FU_type_0::IprAccess 0 0.00% 100.00% |
| system.cpu1.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% |
| system.cpu1.iq.FU_type_0::total 248497 |
| system.cpu1.iq.rate 1.281236 |
| system.cpu1.iq.fu_busy_cnt 472 |
| system.cpu1.iq.fu_busy_rate 0.001899 |
| system.cpu1.iq.int_inst_queue_reads 684523 |
| system.cpu1.iq.int_inst_queue_writes 279437 |
| system.cpu1.iq.int_inst_queue_wakeup_accesses 244623 |
| system.cpu1.iq.fp_inst_queue_reads 0 |
| system.cpu1.iq.fp_inst_queue_writes 88 |
| system.cpu1.iq.fp_inst_queue_wakeup_accesses 0 |
| system.cpu1.iq.int_alu_accesses 248969 |
| system.cpu1.iq.fp_alu_accesses 0 |
| system.cpu1.iew.lsq.thread0.forwLoads 32276 |
| system.cpu1.iew.lsq.thread0.invAddrLoads 0 |
| system.cpu1.iew.lsq.thread0.squashedLoads 4218 |
| system.cpu1.iew.lsq.thread0.ignoredResponses 48 |
| system.cpu1.iew.lsq.thread0.memOrderViolation 39 |
| system.cpu1.iew.lsq.thread0.squashedStores 2578 |
| system.cpu1.iew.lsq.thread0.invAddrSwpfs 0 |
| system.cpu1.iew.lsq.thread0.blockedLoads 0 |
| system.cpu1.iew.lsq.thread0.rescheduledLoads 0 |
| system.cpu1.iew.lsq.thread0.cacheBlocked 0 |
| system.cpu1.iew.iewIdleCycles 0 |
| system.cpu1.iew.iewSquashCycles 2361 |
| system.cpu1.iew.iewBlockCycles 9309 |
| system.cpu1.iew.iewUnblockCycles 53 |
| system.cpu1.iew.iewDispatchedInsts 296855 |
| system.cpu1.iew.iewDispSquashedInsts 287 |
| system.cpu1.iew.iewDispLoadInsts 82743 |
| system.cpu1.iew.iewDispStoreInsts 38627 |
| system.cpu1.iew.iewDispNonSpecInsts 1515 |
| system.cpu1.iew.iewIQFullEvents 28 |
| system.cpu1.iew.iewLSQFullEvents 0 |
| system.cpu1.iew.memOrderViolationEvents 39 |
| system.cpu1.iew.predictedTakenIncorrect 446 |
| system.cpu1.iew.predictedNotTakenIncorrect 2413 |
| system.cpu1.iew.branchMispredicts 2859 |
| system.cpu1.iew.iewExecutedInsts 245962 |
| system.cpu1.iew.iewExecLoadInsts 81205 |
| system.cpu1.iew.iewExecSquashedInsts 2535 |
| system.cpu1.iew.exec_swp 0 |
| system.cpu1.iew.exec_nop 40846 |
| system.cpu1.iew.exec_refs 118541 |
| system.cpu1.iew.exec_branches 51063 |
| system.cpu1.iew.exec_stores 37336 |
| system.cpu1.iew.exec_rate 1.268166 |
| system.cpu1.iew.wb_sent 245120 |
| system.cpu1.iew.wb_count 244623 |
| system.cpu1.iew.wb_producers 136387 |
| system.cpu1.iew.wb_consumers 143829 |
| system.cpu1.iew.wb_rate 1.261262 |
| system.cpu1.iew.wb_fanout 0.948258 |
| system.cpu1.commit.commitSquashedInsts 24565 |
| system.cpu1.commit.commitNonSpecStalls 7653 |
| system.cpu1.commit.branchMispredicts 2283 |
| system.cpu1.commit.committed_per_cycle::samples 182310 |
| system.cpu1.commit.committed_per_cycle::mean 1.493451 |
| system.cpu1.commit.committed_per_cycle::stdev 1.997873 |
| system.cpu1.commit.committed_per_cycle::underflows 0 0.00% 0.00% |
| system.cpu1.commit.committed_per_cycle::0 84529 46.37% 46.37% |
| system.cpu1.commit.committed_per_cycle::1 47318 25.95% 72.32% |
| system.cpu1.commit.committed_per_cycle::2 5367 2.94% 75.26% |
| system.cpu1.commit.committed_per_cycle::3 8292 4.55% 79.81% |
| system.cpu1.commit.committed_per_cycle::4 1281 0.70% 80.52% |
| system.cpu1.commit.committed_per_cycle::5 32483 17.82% 98.33% |
| system.cpu1.commit.committed_per_cycle::6 752 0.41% 98.74% |
| system.cpu1.commit.committed_per_cycle::7 1012 0.56% 99.30% |
| system.cpu1.commit.committed_per_cycle::8 1276 0.70% 100.00% |
| system.cpu1.commit.committed_per_cycle::overflows 0 0.00% 100.00% |
| system.cpu1.commit.committed_per_cycle::min_value 0 |
| system.cpu1.commit.committed_per_cycle::max_value 8 |
| system.cpu1.commit.committed_per_cycle::total 182310 |
| system.cpu1.commit.committedInsts 272271 |
| system.cpu1.commit.committedOps 272271 |
| system.cpu1.commit.swp_count 0 |
| system.cpu1.commit.refs 114574 |
| system.cpu1.commit.loads 78525 |
| system.cpu1.commit.membars 6941 |
| system.cpu1.commit.branches 48947 |
| system.cpu1.commit.fp_insts 0 |
| system.cpu1.commit.int_insts 185648 |
| system.cpu1.commit.function_calls 322 |
| system.cpu1.commit.op_class_0::No_OpClass 39739 14.60% 14.60% |
| system.cpu1.commit.op_class_0::IntAlu 111017 40.77% 55.37% |
| system.cpu1.commit.op_class_0::IntMult 0 0.00% 55.37% |
| system.cpu1.commit.op_class_0::IntDiv 0 0.00% 55.37% |
| system.cpu1.commit.op_class_0::FloatAdd 0 0.00% 55.37% |
| system.cpu1.commit.op_class_0::FloatCmp 0 0.00% 55.37% |
| system.cpu1.commit.op_class_0::FloatCvt 0 0.00% 55.37% |
| system.cpu1.commit.op_class_0::FloatMult 0 0.00% 55.37% |
| system.cpu1.commit.op_class_0::FloatMultAcc 0 0.00% 55.37% |
| system.cpu1.commit.op_class_0::FloatDiv 0 0.00% 55.37% |
| system.cpu1.commit.op_class_0::FloatMisc 0 0.00% 55.37% |
| system.cpu1.commit.op_class_0::FloatSqrt 0 0.00% 55.37% |
| system.cpu1.commit.op_class_0::SimdAdd 0 0.00% 55.37% |
| system.cpu1.commit.op_class_0::SimdAddAcc 0 0.00% 55.37% |
| system.cpu1.commit.op_class_0::SimdAlu 0 0.00% 55.37% |
| system.cpu1.commit.op_class_0::SimdCmp 0 0.00% 55.37% |
| system.cpu1.commit.op_class_0::SimdCvt 0 0.00% 55.37% |
| system.cpu1.commit.op_class_0::SimdMisc 0 0.00% 55.37% |
| system.cpu1.commit.op_class_0::SimdMult 0 0.00% 55.37% |
| system.cpu1.commit.op_class_0::SimdMultAcc 0 0.00% 55.37% |
| system.cpu1.commit.op_class_0::SimdShift 0 0.00% 55.37% |
| system.cpu1.commit.op_class_0::SimdShiftAcc 0 0.00% 55.37% |
| system.cpu1.commit.op_class_0::SimdSqrt 0 0.00% 55.37% |
| system.cpu1.commit.op_class_0::SimdFloatAdd 0 0.00% 55.37% |
| system.cpu1.commit.op_class_0::SimdFloatAlu 0 0.00% 55.37% |
| system.cpu1.commit.op_class_0::SimdFloatCmp 0 0.00% 55.37% |
| system.cpu1.commit.op_class_0::SimdFloatCvt 0 0.00% 55.37% |
| system.cpu1.commit.op_class_0::SimdFloatDiv 0 0.00% 55.37% |
| system.cpu1.commit.op_class_0::SimdFloatMisc 0 0.00% 55.37% |
| system.cpu1.commit.op_class_0::SimdFloatMult 0 0.00% 55.37% |
| system.cpu1.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.37% |
| system.cpu1.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.37% |
| system.cpu1.commit.op_class_0::MemRead 85466 31.39% 86.76% |
| system.cpu1.commit.op_class_0::MemWrite 36049 13.24% 100.00% |
| system.cpu1.commit.op_class_0::FloatMemRead 0 0.00% 100.00% |
| system.cpu1.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% |
| system.cpu1.commit.op_class_0::IprAccess 0 0.00% 100.00% |
| system.cpu1.commit.op_class_0::InstPrefetch 0 0.00% 100.00% |
| system.cpu1.commit.op_class_0::total 272271 |
| system.cpu1.commit.bw_lim_events 1276 |
| system.cpu1.rob.rob_reads 477284 |
| system.cpu1.rob.rob_writes 598384 |
| system.cpu1.timesIdled 242 |
| system.cpu1.idleCycles 6985 |
| system.cpu1.quiesceCycles 49435 |
| system.cpu1.committedInsts 225591 |
| system.cpu1.committedOps 225591 |
| system.cpu1.cpi 0.859746 |
| system.cpu1.cpi_total 0.859746 |
| system.cpu1.ipc 1.163134 |
| system.cpu1.ipc_total 1.163134 |
| system.cpu1.int_regfile_reads 419203 |
| system.cpu1.int_regfile_writes 195886 |
| system.cpu1.fp_regfile_writes 64 |
| system.cpu1.misc_regfile_reads 120419 |
| system.cpu1.misc_regfile_writes 652 |
| system.cpu1.dcache.tags.pwrStateResidencyTicks::UNDEFINED 126524000 |
| system.cpu1.dcache.tags.replacements 0 |
| system.cpu1.dcache.tags.tagsinuse 26.619618 |
| system.cpu1.dcache.tags.total_refs 43145 |
| system.cpu1.dcache.tags.sampled_refs 30 |
| system.cpu1.dcache.tags.avg_refs 1438.166667 |
| system.cpu1.dcache.tags.warmup_cycle 0 |
| system.cpu1.dcache.tags.occ_blocks::cpu1.data 26.619618 |
| system.cpu1.dcache.tags.occ_percent::cpu1.data 0.051991 |
| system.cpu1.dcache.tags.occ_percent::total 0.051991 |
| system.cpu1.dcache.tags.occ_task_id_blocks::1024 30 |
| system.cpu1.dcache.tags.age_task_id_blocks_1024::0 1 |
| system.cpu1.dcache.tags.age_task_id_blocks_1024::1 17 |
| system.cpu1.dcache.tags.age_task_id_blocks_1024::2 12 |
| system.cpu1.dcache.tags.occ_task_id_percent::1024 0.058594 |
| system.cpu1.dcache.tags.tag_accesses 340046 |
| system.cpu1.dcache.tags.data_accesses 340046 |
| system.cpu1.dcache.pwrStateResidencyTicks::UNDEFINED 126524000 |
| system.cpu1.dcache.ReadReq_hits::cpu1.data 48453 |
| system.cpu1.dcache.ReadReq_hits::total 48453 |
| system.cpu1.dcache.WriteReq_hits::cpu1.data 35830 |
| system.cpu1.dcache.WriteReq_hits::total 35830 |
| system.cpu1.dcache.SwapReq_hits::cpu1.data 16 |
| system.cpu1.dcache.SwapReq_hits::total 16 |
| system.cpu1.dcache.demand_hits::cpu1.data 84283 |
| system.cpu1.dcache.demand_hits::total 84283 |
| system.cpu1.dcache.overall_hits::cpu1.data 84283 |
| system.cpu1.dcache.overall_hits::total 84283 |
| system.cpu1.dcache.ReadReq_misses::cpu1.data 447 |
| system.cpu1.dcache.ReadReq_misses::total 447 |
| system.cpu1.dcache.WriteReq_misses::cpu1.data 153 |
| system.cpu1.dcache.WriteReq_misses::total 153 |
| system.cpu1.dcache.SwapReq_misses::cpu1.data 50 |
| system.cpu1.dcache.SwapReq_misses::total 50 |
| system.cpu1.dcache.demand_misses::cpu1.data 600 |
| system.cpu1.dcache.demand_misses::total 600 |
| system.cpu1.dcache.overall_misses::cpu1.data 600 |
| system.cpu1.dcache.overall_misses::total 600 |
| system.cpu1.dcache.ReadReq_miss_latency::cpu1.data 4515500 |
| system.cpu1.dcache.ReadReq_miss_latency::total 4515500 |
| system.cpu1.dcache.WriteReq_miss_latency::cpu1.data 3649500 |
| system.cpu1.dcache.WriteReq_miss_latency::total 3649500 |
| system.cpu1.dcache.SwapReq_miss_latency::cpu1.data 328500 |
| system.cpu1.dcache.SwapReq_miss_latency::total 328500 |
| system.cpu1.dcache.demand_miss_latency::cpu1.data 8165000 |
| system.cpu1.dcache.demand_miss_latency::total 8165000 |
| system.cpu1.dcache.overall_miss_latency::cpu1.data 8165000 |
| system.cpu1.dcache.overall_miss_latency::total 8165000 |
| system.cpu1.dcache.ReadReq_accesses::cpu1.data 48900 |
| system.cpu1.dcache.ReadReq_accesses::total 48900 |
| system.cpu1.dcache.WriteReq_accesses::cpu1.data 35983 |
| system.cpu1.dcache.WriteReq_accesses::total 35983 |
| system.cpu1.dcache.SwapReq_accesses::cpu1.data 66 |
| system.cpu1.dcache.SwapReq_accesses::total 66 |
| system.cpu1.dcache.demand_accesses::cpu1.data 84883 |
| system.cpu1.dcache.demand_accesses::total 84883 |
| system.cpu1.dcache.overall_accesses::cpu1.data 84883 |
| system.cpu1.dcache.overall_accesses::total 84883 |
| system.cpu1.dcache.ReadReq_miss_rate::cpu1.data 0.009141 |
| system.cpu1.dcache.ReadReq_miss_rate::total 0.009141 |
| system.cpu1.dcache.WriteReq_miss_rate::cpu1.data 0.004252 |
| system.cpu1.dcache.WriteReq_miss_rate::total 0.004252 |
| system.cpu1.dcache.SwapReq_miss_rate::cpu1.data 0.757576 |
| system.cpu1.dcache.SwapReq_miss_rate::total 0.757576 |
| system.cpu1.dcache.demand_miss_rate::cpu1.data 0.007069 |
| system.cpu1.dcache.demand_miss_rate::total 0.007069 |
| system.cpu1.dcache.overall_miss_rate::cpu1.data 0.007069 |
| system.cpu1.dcache.overall_miss_rate::total 0.007069 |
| system.cpu1.dcache.ReadReq_avg_miss_latency::cpu1.data 10101.789709 |
| system.cpu1.dcache.ReadReq_avg_miss_latency::total 10101.789709 |
| system.cpu1.dcache.WriteReq_avg_miss_latency::cpu1.data 23852.941176 |
| system.cpu1.dcache.WriteReq_avg_miss_latency::total 23852.941176 |
| system.cpu1.dcache.SwapReq_avg_miss_latency::cpu1.data 6570 |
| system.cpu1.dcache.SwapReq_avg_miss_latency::total 6570 |
| system.cpu1.dcache.demand_avg_miss_latency::cpu1.data 13608.333333 |
| system.cpu1.dcache.demand_avg_miss_latency::total 13608.333333 |
| system.cpu1.dcache.overall_avg_miss_latency::cpu1.data 13608.333333 |
| system.cpu1.dcache.overall_avg_miss_latency::total 13608.333333 |
| system.cpu1.dcache.blocked_cycles::no_mshrs 0 |
| system.cpu1.dcache.blocked_cycles::no_targets 0 |
| system.cpu1.dcache.blocked::no_mshrs 0 |
| system.cpu1.dcache.blocked::no_targets 0 |
| system.cpu1.dcache.avg_blocked_cycles::no_mshrs nan |
| system.cpu1.dcache.avg_blocked_cycles::no_targets nan |
| system.cpu1.dcache.ReadReq_mshr_hits::cpu1.data 284 |
| system.cpu1.dcache.ReadReq_mshr_hits::total 284 |
| system.cpu1.dcache.WriteReq_mshr_hits::cpu1.data 49 |
| system.cpu1.dcache.WriteReq_mshr_hits::total 49 |
| system.cpu1.dcache.SwapReq_mshr_hits::cpu1.data 4 |
| system.cpu1.dcache.SwapReq_mshr_hits::total 4 |
| system.cpu1.dcache.demand_mshr_hits::cpu1.data 333 |
| system.cpu1.dcache.demand_mshr_hits::total 333 |
| system.cpu1.dcache.overall_mshr_hits::cpu1.data 333 |
| system.cpu1.dcache.overall_mshr_hits::total 333 |
| system.cpu1.dcache.ReadReq_mshr_misses::cpu1.data 163 |
| system.cpu1.dcache.ReadReq_mshr_misses::total 163 |
| system.cpu1.dcache.WriteReq_mshr_misses::cpu1.data 104 |
| system.cpu1.dcache.WriteReq_mshr_misses::total 104 |
| system.cpu1.dcache.SwapReq_mshr_misses::cpu1.data 46 |
| system.cpu1.dcache.SwapReq_mshr_misses::total 46 |
| system.cpu1.dcache.demand_mshr_misses::cpu1.data 267 |
| system.cpu1.dcache.demand_mshr_misses::total 267 |
| system.cpu1.dcache.overall_mshr_misses::cpu1.data 267 |
| system.cpu1.dcache.overall_mshr_misses::total 267 |
| system.cpu1.dcache.ReadReq_mshr_miss_latency::cpu1.data 1545000 |
| system.cpu1.dcache.ReadReq_mshr_miss_latency::total 1545000 |
| system.cpu1.dcache.WriteReq_mshr_miss_latency::cpu1.data 1530500 |
| system.cpu1.dcache.WriteReq_mshr_miss_latency::total 1530500 |
| system.cpu1.dcache.SwapReq_mshr_miss_latency::cpu1.data 278500 |
| system.cpu1.dcache.SwapReq_mshr_miss_latency::total 278500 |
| system.cpu1.dcache.demand_mshr_miss_latency::cpu1.data 3075500 |
| system.cpu1.dcache.demand_mshr_miss_latency::total 3075500 |
| system.cpu1.dcache.overall_mshr_miss_latency::cpu1.data 3075500 |
| system.cpu1.dcache.overall_mshr_miss_latency::total 3075500 |
| system.cpu1.dcache.ReadReq_mshr_miss_rate::cpu1.data 0.003333 |
| system.cpu1.dcache.ReadReq_mshr_miss_rate::total 0.003333 |
| system.cpu1.dcache.WriteReq_mshr_miss_rate::cpu1.data 0.002890 |
| system.cpu1.dcache.WriteReq_mshr_miss_rate::total 0.002890 |
| system.cpu1.dcache.SwapReq_mshr_miss_rate::cpu1.data 0.696970 |
| system.cpu1.dcache.SwapReq_mshr_miss_rate::total 0.696970 |
| system.cpu1.dcache.demand_mshr_miss_rate::cpu1.data 0.003146 |
| system.cpu1.dcache.demand_mshr_miss_rate::total 0.003146 |
| system.cpu1.dcache.overall_mshr_miss_rate::cpu1.data 0.003146 |
| system.cpu1.dcache.overall_mshr_miss_rate::total 0.003146 |
| system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::cpu1.data 9478.527607 |
| system.cpu1.dcache.ReadReq_avg_mshr_miss_latency::total 9478.527607 |
| system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::cpu1.data 14716.346154 |
| system.cpu1.dcache.WriteReq_avg_mshr_miss_latency::total 14716.346154 |
| system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::cpu1.data 6054.347826 |
| system.cpu1.dcache.SwapReq_avg_mshr_miss_latency::total 6054.347826 |
| system.cpu1.dcache.demand_avg_mshr_miss_latency::cpu1.data 11518.726592 |
| system.cpu1.dcache.demand_avg_mshr_miss_latency::total 11518.726592 |
| system.cpu1.dcache.overall_avg_mshr_miss_latency::cpu1.data 11518.726592 |
| system.cpu1.dcache.overall_avg_mshr_miss_latency::total 11518.726592 |
| system.cpu1.icache.tags.pwrStateResidencyTicks::UNDEFINED 126524000 |
| system.cpu1.icache.tags.replacements 602 |
| system.cpu1.icache.tags.tagsinuse 99.247443 |
| system.cpu1.icache.tags.total_refs 27667 |
| system.cpu1.icache.tags.sampled_refs 737 |
| system.cpu1.icache.tags.avg_refs 37.540027 |
| system.cpu1.icache.tags.warmup_cycle 0 |
| system.cpu1.icache.tags.occ_blocks::cpu1.inst 99.247443 |
| system.cpu1.icache.tags.occ_percent::cpu1.inst 0.193843 |
| system.cpu1.icache.tags.occ_percent::total 0.193843 |
| system.cpu1.icache.tags.occ_task_id_blocks::1024 135 |
| system.cpu1.icache.tags.age_task_id_blocks_1024::0 18 |
| system.cpu1.icache.tags.age_task_id_blocks_1024::1 99 |
| system.cpu1.icache.tags.age_task_id_blocks_1024::2 18 |
| system.cpu1.icache.tags.occ_task_id_percent::1024 0.263672 |
| system.cpu1.icache.tags.tag_accesses 29299 |
| system.cpu1.icache.tags.data_accesses 29299 |
| system.cpu1.icache.pwrStateResidencyTicks::UNDEFINED 126524000 |
| system.cpu1.icache.ReadReq_hits::cpu1.inst 27667 |
| system.cpu1.icache.ReadReq_hits::total 27667 |
| system.cpu1.icache.demand_hits::cpu1.inst 27667 |
| system.cpu1.icache.demand_hits::total 27667 |
| system.cpu1.icache.overall_hits::cpu1.inst 27667 |
| system.cpu1.icache.overall_hits::total 27667 |
| system.cpu1.icache.ReadReq_misses::cpu1.inst 895 |
| system.cpu1.icache.ReadReq_misses::total 895 |
| system.cpu1.icache.demand_misses::cpu1.inst 895 |
| system.cpu1.icache.demand_misses::total 895 |
| system.cpu1.icache.overall_misses::cpu1.inst 895 |
| system.cpu1.icache.overall_misses::total 895 |
| system.cpu1.icache.ReadReq_miss_latency::cpu1.inst 22011500 |
| system.cpu1.icache.ReadReq_miss_latency::total 22011500 |
| system.cpu1.icache.demand_miss_latency::cpu1.inst 22011500 |
| system.cpu1.icache.demand_miss_latency::total 22011500 |
| system.cpu1.icache.overall_miss_latency::cpu1.inst 22011500 |
| system.cpu1.icache.overall_miss_latency::total 22011500 |
| system.cpu1.icache.ReadReq_accesses::cpu1.inst 28562 |
| system.cpu1.icache.ReadReq_accesses::total 28562 |
| system.cpu1.icache.demand_accesses::cpu1.inst 28562 |
| system.cpu1.icache.demand_accesses::total 28562 |
| system.cpu1.icache.overall_accesses::cpu1.inst 28562 |
| system.cpu1.icache.overall_accesses::total 28562 |
| system.cpu1.icache.ReadReq_miss_rate::cpu1.inst 0.031335 |
| system.cpu1.icache.ReadReq_miss_rate::total 0.031335 |
| system.cpu1.icache.demand_miss_rate::cpu1.inst 0.031335 |
| system.cpu1.icache.demand_miss_rate::total 0.031335 |
| system.cpu1.icache.overall_miss_rate::cpu1.inst 0.031335 |
| system.cpu1.icache.overall_miss_rate::total 0.031335 |
| system.cpu1.icache.ReadReq_avg_miss_latency::cpu1.inst 24593.854749 |
| system.cpu1.icache.ReadReq_avg_miss_latency::total 24593.854749 |
| system.cpu1.icache.demand_avg_miss_latency::cpu1.inst 24593.854749 |
| system.cpu1.icache.demand_avg_miss_latency::total 24593.854749 |
| system.cpu1.icache.overall_avg_miss_latency::cpu1.inst 24593.854749 |
| system.cpu1.icache.overall_avg_miss_latency::total 24593.854749 |
| system.cpu1.icache.blocked_cycles::no_mshrs 240 |
| system.cpu1.icache.blocked_cycles::no_targets 0 |
| system.cpu1.icache.blocked::no_mshrs 8 |
| system.cpu1.icache.blocked::no_targets 0 |
| system.cpu1.icache.avg_blocked_cycles::no_mshrs 30 |
| system.cpu1.icache.avg_blocked_cycles::no_targets nan |
| system.cpu1.icache.writebacks::writebacks 602 |
| system.cpu1.icache.writebacks::total 602 |
| system.cpu1.icache.ReadReq_mshr_hits::cpu1.inst 158 |
| system.cpu1.icache.ReadReq_mshr_hits::total 158 |
| system.cpu1.icache.demand_mshr_hits::cpu1.inst 158 |
| system.cpu1.icache.demand_mshr_hits::total 158 |
| system.cpu1.icache.overall_mshr_hits::cpu1.inst 158 |
| system.cpu1.icache.overall_mshr_hits::total 158 |
| system.cpu1.icache.ReadReq_mshr_misses::cpu1.inst 737 |
| system.cpu1.icache.ReadReq_mshr_misses::total 737 |
| system.cpu1.icache.demand_mshr_misses::cpu1.inst 737 |
| system.cpu1.icache.demand_mshr_misses::total 737 |
| system.cpu1.icache.overall_mshr_misses::cpu1.inst 737 |
| system.cpu1.icache.overall_mshr_misses::total 737 |
| system.cpu1.icache.ReadReq_mshr_miss_latency::cpu1.inst 16836000 |
| system.cpu1.icache.ReadReq_mshr_miss_latency::total 16836000 |
| system.cpu1.icache.demand_mshr_miss_latency::cpu1.inst 16836000 |
| system.cpu1.icache.demand_mshr_miss_latency::total 16836000 |
| system.cpu1.icache.overall_mshr_miss_latency::cpu1.inst 16836000 |
| system.cpu1.icache.overall_mshr_miss_latency::total 16836000 |
| system.cpu1.icache.ReadReq_mshr_miss_rate::cpu1.inst 0.025804 |
| system.cpu1.icache.ReadReq_mshr_miss_rate::total 0.025804 |
| system.cpu1.icache.demand_mshr_miss_rate::cpu1.inst 0.025804 |
| system.cpu1.icache.demand_mshr_miss_rate::total 0.025804 |
| system.cpu1.icache.overall_mshr_miss_rate::cpu1.inst 0.025804 |
| system.cpu1.icache.overall_mshr_miss_rate::total 0.025804 |
| system.cpu1.icache.ReadReq_avg_mshr_miss_latency::cpu1.inst 22843.962008 |
| system.cpu1.icache.ReadReq_avg_mshr_miss_latency::total 22843.962008 |
| system.cpu1.icache.demand_avg_mshr_miss_latency::cpu1.inst 22843.962008 |
| system.cpu1.icache.demand_avg_mshr_miss_latency::total 22843.962008 |
| system.cpu1.icache.overall_avg_mshr_miss_latency::cpu1.inst 22843.962008 |
| system.cpu1.icache.overall_avg_mshr_miss_latency::total 22843.962008 |
| system.cpu2.branchPred.lookups 63005 |
| system.cpu2.branchPred.condPredicted 54943 |
| system.cpu2.branchPred.condIncorrect 2446 |
| system.cpu2.branchPred.BTBLookups 54515 |
| system.cpu2.branchPred.BTBHits 0 |
| system.cpu2.branchPred.BTBCorrect 0 |
| system.cpu2.branchPred.BTBHitPct 0.000000 |
| system.cpu2.branchPred.usedRAS 2009 |
| system.cpu2.branchPred.RASInCorrect 231 |
| system.cpu2.branchPred.indirectLookups 54515 |
| system.cpu2.branchPred.indirectHits 43815 |
| system.cpu2.branchPred.indirectMisses 10700 |
| system.cpu2.branchPredindirectMispredicted 1320 |
| system.cpu2.pwrStateResidencyTicks::ON 126524000 |
| system.cpu2.numCycles 193568 |
| system.cpu2.numWorkItemsStarted 0 |
| system.cpu2.numWorkItemsCompleted 0 |
| system.cpu2.fetch.icacheStallCycles 41212 |
| system.cpu2.fetch.Insts 337111 |
| system.cpu2.fetch.Branches 63005 |
| system.cpu2.fetch.predictedBranches 45824 |
| system.cpu2.fetch.Cycles 146186 |
| system.cpu2.fetch.SquashCycles 5049 |
| system.cpu2.fetch.MiscStallCycles 3 |
| system.cpu2.fetch.NoActiveThreadStallCycles 10 |
| system.cpu2.fetch.PendingTrapStallCycles 1881 |
| system.cpu2.fetch.CacheLines 30662 |
| system.cpu2.fetch.IcacheSquashes 928 |
| system.cpu2.fetch.rateDist::samples 191816 |
| system.cpu2.fetch.rateDist::mean 1.757471 |
| system.cpu2.fetch.rateDist::stdev 2.316309 |
| system.cpu2.fetch.rateDist::underflows 0 0.00% 0.00% |
| system.cpu2.fetch.rateDist::0 78288 40.81% 40.81% |
| system.cpu2.fetch.rateDist::1 56335 29.37% 70.18% |
| system.cpu2.fetch.rateDist::2 9442 4.92% 75.11% |
| system.cpu2.fetch.rateDist::3 3538 1.84% 76.95% |
| system.cpu2.fetch.rateDist::4 653 0.34% 77.29% |
| system.cpu2.fetch.rateDist::5 32047 16.71% 94.00% |
| system.cpu2.fetch.rateDist::6 1150 0.60% 94.60% |
| system.cpu2.fetch.rateDist::7 1373 0.72% 95.31% |
| system.cpu2.fetch.rateDist::8 8990 4.69% 100.00% |
| system.cpu2.fetch.rateDist::overflows 0 0.00% 100.00% |
| system.cpu2.fetch.rateDist::min_value 0 |
| system.cpu2.fetch.rateDist::max_value 8 |
| system.cpu2.fetch.rateDist::total 191816 |
| system.cpu2.fetch.branchRate 0.325493 |
| system.cpu2.fetch.rate 1.741564 |
| system.cpu2.decode.IdleCycles 22511 |
| system.cpu2.decode.BlockedCycles 80270 |
| system.cpu2.decode.RunCycles 81305 |
| system.cpu2.decode.UnblockCycles 5196 |
| system.cpu2.decode.SquashCycles 2524 |
| system.cpu2.decode.DecodedInsts 304951 |
| system.cpu2.rename.SquashCycles 2524 |
| system.cpu2.rename.IdleCycles 23572 |
| system.cpu2.rename.BlockCycles 39907 |
| system.cpu2.rename.serializeStallCycles 13834 |
| system.cpu2.rename.RunCycles 82651 |
| system.cpu2.rename.UnblockCycles 29318 |
| system.cpu2.rename.RenamedInsts 297990 |
| system.cpu2.rename.IQFullEvents 25746 |
| system.cpu2.rename.LQFullEvents 17 |
| system.cpu2.rename.FullRegisterEvents 2 |
| system.cpu2.rename.RenamedOperands 207037 |
| system.cpu2.rename.RenameLookups 557824 |
| system.cpu2.rename.int_rename_lookups 436197 |
| system.cpu2.rename.fp_rename_lookups 20 |
| system.cpu2.rename.CommittedMaps 176797 |
| system.cpu2.rename.UndoneMaps 30240 |
| system.cpu2.rename.serializingInsts 1683 |
| system.cpu2.rename.tempSerializingInsts 1817 |
| system.cpu2.rename.skidInsts 35305 |
| system.cpu2.memDep0.insertedLoads 79616 |
| system.cpu2.memDep0.insertedStores 36437 |
| system.cpu2.memDep0.conflictingLoads 38372 |
| system.cpu2.memDep0.conflictingStores 30080 |
| system.cpu2.iq.iqInstsAdded 239894 |
| system.cpu2.iq.iqNonSpecInstsAdded 9906 |
| system.cpu2.iq.iqInstsIssued 241219 |
| system.cpu2.iq.iqSquashedInstsIssued 120 |
| system.cpu2.iq.iqSquashedInstsExamined 26152 |
| system.cpu2.iq.iqSquashedOperandsExamined 21212 |
| system.cpu2.iq.iqSquashedNonSpecRemoved 1309 |
| system.cpu2.iq.issued_per_cycle::samples 191816 |
| system.cpu2.iq.issued_per_cycle::mean 1.257554 |
| system.cpu2.iq.issued_per_cycle::stdev 1.379653 |
| system.cpu2.iq.issued_per_cycle::underflows 0 0.00% 0.00% |
| system.cpu2.iq.issued_per_cycle::0 83659 43.61% 43.61% |
| system.cpu2.iq.issued_per_cycle::1 31014 16.17% 59.78% |
| system.cpu2.iq.issued_per_cycle::2 35021 18.26% 78.04% |
| system.cpu2.iq.issued_per_cycle::3 34852 18.17% 96.21% |
| system.cpu2.iq.issued_per_cycle::4 3649 1.90% 98.11% |
| system.cpu2.iq.issued_per_cycle::5 1791 0.93% 99.05% |
| system.cpu2.iq.issued_per_cycle::6 1085 0.57% 99.61% |
| system.cpu2.iq.issued_per_cycle::7 414 0.22% 99.83% |
| system.cpu2.iq.issued_per_cycle::8 331 0.17% 100.00% |
| system.cpu2.iq.issued_per_cycle::overflows 0 0.00% 100.00% |
| system.cpu2.iq.issued_per_cycle::min_value 0 |
| system.cpu2.iq.issued_per_cycle::max_value 8 |
| system.cpu2.iq.issued_per_cycle::total 191816 |
| system.cpu2.iq.fu_full::No_OpClass 0 0.00% 0.00% |
| system.cpu2.iq.fu_full::IntAlu 208 41.52% 41.52% |
| system.cpu2.iq.fu_full::IntMult 0 0.00% 41.52% |
| system.cpu2.iq.fu_full::IntDiv 0 0.00% 41.52% |
| system.cpu2.iq.fu_full::FloatAdd 0 0.00% 41.52% |
| system.cpu2.iq.fu_full::FloatCmp 0 0.00% 41.52% |
| system.cpu2.iq.fu_full::FloatCvt 0 0.00% 41.52% |
| system.cpu2.iq.fu_full::FloatMult 0 0.00% 41.52% |
| system.cpu2.iq.fu_full::FloatMultAcc 0 0.00% 41.52% |
| system.cpu2.iq.fu_full::FloatDiv 0 0.00% 41.52% |
| system.cpu2.iq.fu_full::FloatMisc 0 0.00% 41.52% |
| system.cpu2.iq.fu_full::FloatSqrt 0 0.00% 41.52% |
| system.cpu2.iq.fu_full::SimdAdd 0 0.00% 41.52% |
| system.cpu2.iq.fu_full::SimdAddAcc 0 0.00% 41.52% |
| system.cpu2.iq.fu_full::SimdAlu 0 0.00% 41.52% |
| system.cpu2.iq.fu_full::SimdCmp 0 0.00% 41.52% |
| system.cpu2.iq.fu_full::SimdCvt 0 0.00% 41.52% |
| system.cpu2.iq.fu_full::SimdMisc 0 0.00% 41.52% |
| system.cpu2.iq.fu_full::SimdMult 0 0.00% 41.52% |
| system.cpu2.iq.fu_full::SimdMultAcc 0 0.00% 41.52% |
| system.cpu2.iq.fu_full::SimdShift 0 0.00% 41.52% |
| system.cpu2.iq.fu_full::SimdShiftAcc 0 0.00% 41.52% |
| system.cpu2.iq.fu_full::SimdSqrt 0 0.00% 41.52% |
| system.cpu2.iq.fu_full::SimdFloatAdd 0 0.00% 41.52% |
| system.cpu2.iq.fu_full::SimdFloatAlu 0 0.00% 41.52% |
| system.cpu2.iq.fu_full::SimdFloatCmp 0 0.00% 41.52% |
| system.cpu2.iq.fu_full::SimdFloatCvt 0 0.00% 41.52% |
| system.cpu2.iq.fu_full::SimdFloatDiv 0 0.00% 41.52% |
| system.cpu2.iq.fu_full::SimdFloatMisc 0 0.00% 41.52% |
| system.cpu2.iq.fu_full::SimdFloatMult 0 0.00% 41.52% |
| system.cpu2.iq.fu_full::SimdFloatMultAcc 0 0.00% 41.52% |
| system.cpu2.iq.fu_full::SimdFloatSqrt 0 0.00% 41.52% |
| system.cpu2.iq.fu_full::MemRead 64 12.77% 54.29% |
| system.cpu2.iq.fu_full::MemWrite 229 45.71% 100.00% |
| system.cpu2.iq.fu_full::FloatMemRead 0 0.00% 100.00% |
| system.cpu2.iq.fu_full::FloatMemWrite 0 0.00% 100.00% |
| system.cpu2.iq.fu_full::IprAccess 0 0.00% 100.00% |
| system.cpu2.iq.fu_full::InstPrefetch 0 0.00% 100.00% |
| system.cpu2.iq.FU_type_0::No_OpClass 0 0.00% 0.00% |
| system.cpu2.iq.FU_type_0::IntAlu 119551 49.56% 49.56% |
| system.cpu2.iq.FU_type_0::IntMult 0 0.00% 49.56% |
| system.cpu2.iq.FU_type_0::IntDiv 0 0.00% 49.56% |
| system.cpu2.iq.FU_type_0::FloatAdd 0 0.00% 49.56% |
| system.cpu2.iq.FU_type_0::FloatCmp 0 0.00% 49.56% |
| system.cpu2.iq.FU_type_0::FloatCvt 0 0.00% 49.56% |
| system.cpu2.iq.FU_type_0::FloatMult 0 0.00% 49.56% |
| system.cpu2.iq.FU_type_0::FloatMultAcc 0 0.00% 49.56% |
| system.cpu2.iq.FU_type_0::FloatDiv 0 0.00% 49.56% |
| system.cpu2.iq.FU_type_0::FloatMisc 0 0.00% 49.56% |
| system.cpu2.iq.FU_type_0::FloatSqrt 0 0.00% 49.56% |
| system.cpu2.iq.FU_type_0::SimdAdd 0 0.00% 49.56% |
| system.cpu2.iq.FU_type_0::SimdAddAcc 0 0.00% 49.56% |
| system.cpu2.iq.FU_type_0::SimdAlu 0 0.00% 49.56% |
| system.cpu2.iq.FU_type_0::SimdCmp 0 0.00% 49.56% |
| system.cpu2.iq.FU_type_0::SimdCvt 0 0.00% 49.56% |
| system.cpu2.iq.FU_type_0::SimdMisc 0 0.00% 49.56% |
| system.cpu2.iq.FU_type_0::SimdMult 0 0.00% 49.56% |
| system.cpu2.iq.FU_type_0::SimdMultAcc 0 0.00% 49.56% |
| system.cpu2.iq.FU_type_0::SimdShift 0 0.00% 49.56% |
| system.cpu2.iq.FU_type_0::SimdShiftAcc 0 0.00% 49.56% |
| system.cpu2.iq.FU_type_0::SimdSqrt 0 0.00% 49.56% |
| system.cpu2.iq.FU_type_0::SimdFloatAdd 0 0.00% 49.56% |
| system.cpu2.iq.FU_type_0::SimdFloatAlu 0 0.00% 49.56% |
| system.cpu2.iq.FU_type_0::SimdFloatCmp 0 0.00% 49.56% |
| system.cpu2.iq.FU_type_0::SimdFloatCvt 0 0.00% 49.56% |
| system.cpu2.iq.FU_type_0::SimdFloatDiv 0 0.00% 49.56% |
| system.cpu2.iq.FU_type_0::SimdFloatMisc 0 0.00% 49.56% |
| system.cpu2.iq.FU_type_0::SimdFloatMult 0 0.00% 49.56% |
| system.cpu2.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 49.56% |
| system.cpu2.iq.FU_type_0::SimdFloatSqrt 0 0.00% 49.56% |
| system.cpu2.iq.FU_type_0::MemRead 86276 35.77% 85.33% |
| system.cpu2.iq.FU_type_0::MemWrite 35392 14.67% 100.00% |
| system.cpu2.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% |
| system.cpu2.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% |
| system.cpu2.iq.FU_type_0::IprAccess 0 0.00% 100.00% |
| system.cpu2.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% |
| system.cpu2.iq.FU_type_0::total 241219 |
| system.cpu2.iq.rate 1.246172 |
| system.cpu2.iq.fu_busy_cnt 501 |
| system.cpu2.iq.fu_busy_rate 0.002077 |
| system.cpu2.iq.int_inst_queue_reads 674875 |
| system.cpu2.iq.int_inst_queue_writes 275950 |
| system.cpu2.iq.int_inst_queue_wakeup_accesses 237037 |
| system.cpu2.iq.fp_inst_queue_reads 0 |
| system.cpu2.iq.fp_inst_queue_writes 40 |
| system.cpu2.iq.fp_inst_queue_wakeup_accesses 0 |
| system.cpu2.iq.int_alu_accesses 241720 |
| system.cpu2.iq.fp_alu_accesses 0 |
| system.cpu2.iew.lsq.thread0.forwLoads 29936 |
| system.cpu2.iew.lsq.thread0.invAddrLoads 0 |
| system.cpu2.iew.lsq.thread0.squashedLoads 4843 |
| system.cpu2.iew.lsq.thread0.ignoredResponses 35 |
| system.cpu2.iew.lsq.thread0.memOrderViolation 38 |
| system.cpu2.iew.lsq.thread0.squashedStores 2724 |
| system.cpu2.iew.lsq.thread0.invAddrSwpfs 0 |
| system.cpu2.iew.lsq.thread0.blockedLoads 0 |
| system.cpu2.iew.lsq.thread0.rescheduledLoads 0 |
| system.cpu2.iew.lsq.thread0.cacheBlocked 0 |
| system.cpu2.iew.iewIdleCycles 0 |
| system.cpu2.iew.iewSquashCycles 2524 |
| system.cpu2.iew.iewBlockCycles 10427 |
| system.cpu2.iew.iewUnblockCycles 59 |
| system.cpu2.iew.iewDispatchedInsts 289447 |
| system.cpu2.iew.iewDispSquashedInsts 340 |
| system.cpu2.iew.iewDispLoadInsts 79616 |
| system.cpu2.iew.iewDispStoreInsts 36437 |
| system.cpu2.iew.iewDispNonSpecInsts 1558 |
| system.cpu2.iew.iewIQFullEvents 36 |
| system.cpu2.iew.iewLSQFullEvents 0 |
| system.cpu2.iew.memOrderViolationEvents 38 |
| system.cpu2.iew.predictedTakenIncorrect 449 |
| system.cpu2.iew.predictedNotTakenIncorrect 2607 |
| system.cpu2.iew.branchMispredicts 3056 |
| system.cpu2.iew.iewExecutedInsts 238568 |
| system.cpu2.iew.iewExecLoadInsts 77774 |
| system.cpu2.iew.iewExecSquashedInsts 2651 |
| system.cpu2.iew.exec_swp 0 |
| system.cpu2.iew.exec_nop 39647 |
| system.cpu2.iew.exec_refs 112834 |
| system.cpu2.iew.exec_branches 49845 |
| system.cpu2.iew.exec_stores 35060 |
| system.cpu2.iew.exec_rate 1.232476 |
| system.cpu2.iew.wb_sent 237626 |
| system.cpu2.iew.wb_count 237037 |
| system.cpu2.iew.wb_producers 130856 |
| system.cpu2.iew.wb_consumers 138405 |
| system.cpu2.iew.wb_rate 1.224567 |
| system.cpu2.iew.wb_fanout 0.945457 |
| system.cpu2.commit.commitSquashedInsts 27430 |
| system.cpu2.commit.commitNonSpecStalls 8597 |
| system.cpu2.commit.branchMispredicts 2446 |
| system.cpu2.commit.committed_per_cycle::samples 186682 |
| system.cpu2.commit.committed_per_cycle::mean 1.403387 |
| system.cpu2.commit.committed_per_cycle::stdev 1.956532 |
| system.cpu2.commit.committed_per_cycle::underflows 0 0.00% 0.00% |
| system.cpu2.commit.committed_per_cycle::0 91634 49.09% 49.09% |
| system.cpu2.commit.committed_per_cycle::1 46034 24.66% 73.74% |
| system.cpu2.commit.committed_per_cycle::2 5345 2.86% 76.61% |
| system.cpu2.commit.committed_per_cycle::3 9142 4.90% 81.50% |
| system.cpu2.commit.committed_per_cycle::4 1340 0.72% 82.22% |
| system.cpu2.commit.committed_per_cycle::5 30155 16.15% 98.38% |
| system.cpu2.commit.committed_per_cycle::6 771 0.41% 98.79% |
| system.cpu2.commit.committed_per_cycle::7 1012 0.54% 99.33% |
| system.cpu2.commit.committed_per_cycle::8 1249 0.67% 100.00% |
| system.cpu2.commit.committed_per_cycle::overflows 0 0.00% 100.00% |
| system.cpu2.commit.committed_per_cycle::min_value 0 |
| system.cpu2.commit.committed_per_cycle::max_value 8 |
| system.cpu2.commit.committed_per_cycle::total 186682 |
| system.cpu2.commit.committedInsts 261987 |
| system.cpu2.commit.committedOps 261987 |
| system.cpu2.commit.swp_count 0 |
| system.cpu2.commit.refs 108486 |
| system.cpu2.commit.loads 74773 |
| system.cpu2.commit.membars 7877 |
| system.cpu2.commit.branches 47555 |
| system.cpu2.commit.fp_insts 0 |
| system.cpu2.commit.int_insts 178156 |
| system.cpu2.commit.function_calls 322 |
| system.cpu2.commit.op_class_0::No_OpClass 38339 14.63% 14.63% |
| system.cpu2.commit.op_class_0::IntAlu 107285 40.95% 55.58% |
| system.cpu2.commit.op_class_0::IntMult 0 0.00% 55.58% |
| system.cpu2.commit.op_class_0::IntDiv 0 0.00% 55.58% |
| system.cpu2.commit.op_class_0::FloatAdd 0 0.00% 55.58% |
| system.cpu2.commit.op_class_0::FloatCmp 0 0.00% 55.58% |
| system.cpu2.commit.op_class_0::FloatCvt 0 0.00% 55.58% |
| system.cpu2.commit.op_class_0::FloatMult 0 0.00% 55.58% |
| system.cpu2.commit.op_class_0::FloatMultAcc 0 0.00% 55.58% |
| system.cpu2.commit.op_class_0::FloatDiv 0 0.00% 55.58% |
| system.cpu2.commit.op_class_0::FloatMisc 0 0.00% 55.58% |
| system.cpu2.commit.op_class_0::FloatSqrt 0 0.00% 55.58% |
| system.cpu2.commit.op_class_0::SimdAdd 0 0.00% 55.58% |
| system.cpu2.commit.op_class_0::SimdAddAcc 0 0.00% 55.58% |
| system.cpu2.commit.op_class_0::SimdAlu 0 0.00% 55.58% |
| system.cpu2.commit.op_class_0::SimdCmp 0 0.00% 55.58% |
| system.cpu2.commit.op_class_0::SimdCvt 0 0.00% 55.58% |
| system.cpu2.commit.op_class_0::SimdMisc 0 0.00% 55.58% |
| system.cpu2.commit.op_class_0::SimdMult 0 0.00% 55.58% |
| system.cpu2.commit.op_class_0::SimdMultAcc 0 0.00% 55.58% |
| system.cpu2.commit.op_class_0::SimdShift 0 0.00% 55.58% |
| system.cpu2.commit.op_class_0::SimdShiftAcc 0 0.00% 55.58% |
| system.cpu2.commit.op_class_0::SimdSqrt 0 0.00% 55.58% |
| system.cpu2.commit.op_class_0::SimdFloatAdd 0 0.00% 55.58% |
| system.cpu2.commit.op_class_0::SimdFloatAlu 0 0.00% 55.58% |
| system.cpu2.commit.op_class_0::SimdFloatCmp 0 0.00% 55.58% |
| system.cpu2.commit.op_class_0::SimdFloatCvt 0 0.00% 55.58% |
| system.cpu2.commit.op_class_0::SimdFloatDiv 0 0.00% 55.58% |
| system.cpu2.commit.op_class_0::SimdFloatMisc 0 0.00% 55.58% |
| system.cpu2.commit.op_class_0::SimdFloatMult 0 0.00% 55.58% |
| system.cpu2.commit.op_class_0::SimdFloatMultAcc 0 0.00% 55.58% |
| system.cpu2.commit.op_class_0::SimdFloatSqrt 0 0.00% 55.58% |
| system.cpu2.commit.op_class_0::MemRead 82650 31.55% 87.13% |
| system.cpu2.commit.op_class_0::MemWrite 33713 12.87% 100.00% |
| system.cpu2.commit.op_class_0::FloatMemRead 0 0.00% 100.00% |
| system.cpu2.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% |
| system.cpu2.commit.op_class_0::IprAccess 0 0.00% 100.00% |
| system.cpu2.commit.op_class_0::InstPrefetch 0 0.00% 100.00% |
| system.cpu2.commit.op_class_0::total 261987 |
| system.cpu2.commit.bw_lim_events 1249 |
| system.cpu2.rob.rob_reads 474264 |
| system.cpu2.rob.rob_writes 584030 |
| system.cpu2.timesIdled 214 |
| system.cpu2.idleCycles 1752 |
| system.cpu2.quiesceCycles 49819 |
| system.cpu2.committedInsts 215771 |
| system.cpu2.committedOps 215771 |
| system.cpu2.cpi 0.897099 |
| system.cpu2.cpi_total 0.897099 |
| system.cpu2.ipc 1.114704 |
| system.cpu2.ipc_total 1.114704 |
| system.cpu2.int_regfile_reads 403346 |
| system.cpu2.int_regfile_writes 188790 |
| system.cpu2.fp_regfile_writes 64 |
| system.cpu2.misc_regfile_reads 114754 |
| system.cpu2.misc_regfile_writes 652 |
| system.cpu2.dcache.tags.pwrStateResidencyTicks::UNDEFINED 126524000 |
| system.cpu2.dcache.tags.replacements 0 |
| system.cpu2.dcache.tags.tagsinuse 24.506015 |
| system.cpu2.dcache.tags.total_refs 40898 |
| system.cpu2.dcache.tags.sampled_refs 29 |
| system.cpu2.dcache.tags.avg_refs 1410.275862 |
| system.cpu2.dcache.tags.warmup_cycle 0 |
| system.cpu2.dcache.tags.occ_blocks::cpu2.data 24.506015 |
| system.cpu2.dcache.tags.occ_percent::cpu2.data 0.047863 |
| system.cpu2.dcache.tags.occ_percent::total 0.047863 |
| system.cpu2.dcache.tags.occ_task_id_blocks::1024 29 |
| system.cpu2.dcache.tags.age_task_id_blocks_1024::1 25 |
| system.cpu2.dcache.tags.age_task_id_blocks_1024::2 4 |
| system.cpu2.dcache.tags.occ_task_id_percent::1024 0.056641 |
| system.cpu2.dcache.tags.tag_accesses 326280 |
| system.cpu2.dcache.tags.data_accesses 326280 |
| system.cpu2.dcache.pwrStateResidencyTicks::UNDEFINED 126524000 |
| system.cpu2.dcache.ReadReq_hits::cpu2.data 47272 |
| system.cpu2.dcache.ReadReq_hits::total 47272 |
| system.cpu2.dcache.WriteReq_hits::cpu2.data 33497 |
| system.cpu2.dcache.WriteReq_hits::total 33497 |
| system.cpu2.dcache.SwapReq_hits::cpu2.data 12 |
| system.cpu2.dcache.SwapReq_hits::total 12 |
| system.cpu2.dcache.demand_hits::cpu2.data 80769 |
| system.cpu2.dcache.demand_hits::total 80769 |
| system.cpu2.dcache.overall_hits::cpu2.data 80769 |
| system.cpu2.dcache.overall_hits::total 80769 |
| system.cpu2.dcache.ReadReq_misses::cpu2.data 517 |
| system.cpu2.dcache.ReadReq_misses::total 517 |
| system.cpu2.dcache.WriteReq_misses::cpu2.data 142 |
| system.cpu2.dcache.WriteReq_misses::total 142 |
| system.cpu2.dcache.SwapReq_misses::cpu2.data 62 |
| system.cpu2.dcache.SwapReq_misses::total 62 |
| system.cpu2.dcache.demand_misses::cpu2.data 659 |
| system.cpu2.dcache.demand_misses::total 659 |
| system.cpu2.dcache.overall_misses::cpu2.data 659 |
| system.cpu2.dcache.overall_misses::total 659 |
| system.cpu2.dcache.ReadReq_miss_latency::cpu2.data 4039000 |
| system.cpu2.dcache.ReadReq_miss_latency::total 4039000 |
| system.cpu2.dcache.WriteReq_miss_latency::cpu2.data 3186000 |
| system.cpu2.dcache.WriteReq_miss_latency::total 3186000 |
| system.cpu2.dcache.SwapReq_miss_latency::cpu2.data 386500 |
| system.cpu2.dcache.SwapReq_miss_latency::total 386500 |
| system.cpu2.dcache.demand_miss_latency::cpu2.data 7225000 |
| system.cpu2.dcache.demand_miss_latency::total 7225000 |
| system.cpu2.dcache.overall_miss_latency::cpu2.data 7225000 |
| system.cpu2.dcache.overall_miss_latency::total 7225000 |
| system.cpu2.dcache.ReadReq_accesses::cpu2.data 47789 |
| system.cpu2.dcache.ReadReq_accesses::total 47789 |
| system.cpu2.dcache.WriteReq_accesses::cpu2.data 33639 |
| system.cpu2.dcache.WriteReq_accesses::total 33639 |
| system.cpu2.dcache.SwapReq_accesses::cpu2.data 74 |
| system.cpu2.dcache.SwapReq_accesses::total 74 |
| system.cpu2.dcache.demand_accesses::cpu2.data 81428 |
| system.cpu2.dcache.demand_accesses::total 81428 |
| system.cpu2.dcache.overall_accesses::cpu2.data 81428 |
| system.cpu2.dcache.overall_accesses::total 81428 |
| system.cpu2.dcache.ReadReq_miss_rate::cpu2.data 0.010818 |
| system.cpu2.dcache.ReadReq_miss_rate::total 0.010818 |
| system.cpu2.dcache.WriteReq_miss_rate::cpu2.data 0.004221 |
| system.cpu2.dcache.WriteReq_miss_rate::total 0.004221 |
| system.cpu2.dcache.SwapReq_miss_rate::cpu2.data 0.837838 |
| system.cpu2.dcache.SwapReq_miss_rate::total 0.837838 |
| system.cpu2.dcache.demand_miss_rate::cpu2.data 0.008093 |
| system.cpu2.dcache.demand_miss_rate::total 0.008093 |
| system.cpu2.dcache.overall_miss_rate::cpu2.data 0.008093 |
| system.cpu2.dcache.overall_miss_rate::total 0.008093 |
| system.cpu2.dcache.ReadReq_avg_miss_latency::cpu2.data 7812.379110 |
| system.cpu2.dcache.ReadReq_avg_miss_latency::total 7812.379110 |
| system.cpu2.dcache.WriteReq_avg_miss_latency::cpu2.data 22436.619718 |
| system.cpu2.dcache.WriteReq_avg_miss_latency::total 22436.619718 |
| system.cpu2.dcache.SwapReq_avg_miss_latency::cpu2.data 6233.870968 |
| system.cpu2.dcache.SwapReq_avg_miss_latency::total 6233.870968 |
| system.cpu2.dcache.demand_avg_miss_latency::cpu2.data 10963.581184 |
| system.cpu2.dcache.demand_avg_miss_latency::total 10963.581184 |
| system.cpu2.dcache.overall_avg_miss_latency::cpu2.data 10963.581184 |
| system.cpu2.dcache.overall_avg_miss_latency::total 10963.581184 |
| system.cpu2.dcache.blocked_cycles::no_mshrs 0 |
| system.cpu2.dcache.blocked_cycles::no_targets 0 |
| system.cpu2.dcache.blocked::no_mshrs 0 |
| system.cpu2.dcache.blocked::no_targets 0 |
| system.cpu2.dcache.avg_blocked_cycles::no_mshrs nan |
| system.cpu2.dcache.avg_blocked_cycles::no_targets nan |
| system.cpu2.dcache.ReadReq_mshr_hits::cpu2.data 341 |
| system.cpu2.dcache.ReadReq_mshr_hits::total 341 |
| system.cpu2.dcache.WriteReq_mshr_hits::cpu2.data 36 |
| system.cpu2.dcache.WriteReq_mshr_hits::total 36 |
| system.cpu2.dcache.demand_mshr_hits::cpu2.data 377 |
| system.cpu2.dcache.demand_mshr_hits::total 377 |
| system.cpu2.dcache.overall_mshr_hits::cpu2.data 377 |
| system.cpu2.dcache.overall_mshr_hits::total 377 |
| system.cpu2.dcache.ReadReq_mshr_misses::cpu2.data 176 |
| system.cpu2.dcache.ReadReq_mshr_misses::total 176 |
| system.cpu2.dcache.WriteReq_mshr_misses::cpu2.data 106 |
| system.cpu2.dcache.WriteReq_mshr_misses::total 106 |
| system.cpu2.dcache.SwapReq_mshr_misses::cpu2.data 62 |
| system.cpu2.dcache.SwapReq_mshr_misses::total 62 |
| system.cpu2.dcache.demand_mshr_misses::cpu2.data 282 |
| system.cpu2.dcache.demand_mshr_misses::total 282 |
| system.cpu2.dcache.overall_mshr_misses::cpu2.data 282 |
| system.cpu2.dcache.overall_mshr_misses::total 282 |
| system.cpu2.dcache.ReadReq_mshr_miss_latency::cpu2.data 1172500 |
| system.cpu2.dcache.ReadReq_mshr_miss_latency::total 1172500 |
| system.cpu2.dcache.WriteReq_mshr_miss_latency::cpu2.data 1650500 |
| system.cpu2.dcache.WriteReq_mshr_miss_latency::total 1650500 |
| system.cpu2.dcache.SwapReq_mshr_miss_latency::cpu2.data 324500 |
| system.cpu2.dcache.SwapReq_mshr_miss_latency::total 324500 |
| system.cpu2.dcache.demand_mshr_miss_latency::cpu2.data 2823000 |
| system.cpu2.dcache.demand_mshr_miss_latency::total 2823000 |
| system.cpu2.dcache.overall_mshr_miss_latency::cpu2.data 2823000 |
| system.cpu2.dcache.overall_mshr_miss_latency::total 2823000 |
| system.cpu2.dcache.ReadReq_mshr_miss_rate::cpu2.data 0.003683 |
| system.cpu2.dcache.ReadReq_mshr_miss_rate::total 0.003683 |
| system.cpu2.dcache.WriteReq_mshr_miss_rate::cpu2.data 0.003151 |
| system.cpu2.dcache.WriteReq_mshr_miss_rate::total 0.003151 |
| system.cpu2.dcache.SwapReq_mshr_miss_rate::cpu2.data 0.837838 |
| system.cpu2.dcache.SwapReq_mshr_miss_rate::total 0.837838 |
| system.cpu2.dcache.demand_mshr_miss_rate::cpu2.data 0.003463 |
| system.cpu2.dcache.demand_mshr_miss_rate::total 0.003463 |
| system.cpu2.dcache.overall_mshr_miss_rate::cpu2.data 0.003463 |
| system.cpu2.dcache.overall_mshr_miss_rate::total 0.003463 |
| system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::cpu2.data 6661.931818 |
| system.cpu2.dcache.ReadReq_avg_mshr_miss_latency::total 6661.931818 |
| system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::cpu2.data 15570.754717 |
| system.cpu2.dcache.WriteReq_avg_mshr_miss_latency::total 15570.754717 |
| system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::cpu2.data 5233.870968 |
| system.cpu2.dcache.SwapReq_avg_mshr_miss_latency::total 5233.870968 |
| system.cpu2.dcache.demand_avg_mshr_miss_latency::cpu2.data 10010.638298 |
| system.cpu2.dcache.demand_avg_mshr_miss_latency::total 10010.638298 |
| system.cpu2.dcache.overall_avg_mshr_miss_latency::cpu2.data 10010.638298 |
| system.cpu2.dcache.overall_avg_mshr_miss_latency::total 10010.638298 |
| system.cpu2.icache.tags.pwrStateResidencyTicks::UNDEFINED 126524000 |
| system.cpu2.icache.tags.replacements 533 |
| system.cpu2.icache.tags.tagsinuse 93.527122 |
| system.cpu2.icache.tags.total_refs 29858 |
| system.cpu2.icache.tags.sampled_refs 668 |
| system.cpu2.icache.tags.avg_refs 44.697605 |
| system.cpu2.icache.tags.warmup_cycle 0 |
| system.cpu2.icache.tags.occ_blocks::cpu2.inst 93.527122 |
| system.cpu2.icache.tags.occ_percent::cpu2.inst 0.182670 |
| system.cpu2.icache.tags.occ_percent::total 0.182670 |
| system.cpu2.icache.tags.occ_task_id_blocks::1024 135 |
| system.cpu2.icache.tags.age_task_id_blocks_1024::0 16 |
| system.cpu2.icache.tags.age_task_id_blocks_1024::1 107 |
| system.cpu2.icache.tags.age_task_id_blocks_1024::2 12 |
| system.cpu2.icache.tags.occ_task_id_percent::1024 0.263672 |
| system.cpu2.icache.tags.tag_accesses 31330 |
| system.cpu2.icache.tags.data_accesses 31330 |
| system.cpu2.icache.pwrStateResidencyTicks::UNDEFINED 126524000 |
| system.cpu2.icache.ReadReq_hits::cpu2.inst 29858 |
| system.cpu2.icache.ReadReq_hits::total 29858 |
| system.cpu2.icache.demand_hits::cpu2.inst 29858 |
| system.cpu2.icache.demand_hits::total 29858 |
| system.cpu2.icache.overall_hits::cpu2.inst 29858 |
| system.cpu2.icache.overall_hits::total 29858 |
| system.cpu2.icache.ReadReq_misses::cpu2.inst 804 |
| system.cpu2.icache.ReadReq_misses::total 804 |
| system.cpu2.icache.demand_misses::cpu2.inst 804 |
| system.cpu2.icache.demand_misses::total 804 |
| system.cpu2.icache.overall_misses::cpu2.inst 804 |
| system.cpu2.icache.overall_misses::total 804 |
| system.cpu2.icache.ReadReq_miss_latency::cpu2.inst 12745500 |
| system.cpu2.icache.ReadReq_miss_latency::total 12745500 |
| system.cpu2.icache.demand_miss_latency::cpu2.inst 12745500 |
| system.cpu2.icache.demand_miss_latency::total 12745500 |
| system.cpu2.icache.overall_miss_latency::cpu2.inst 12745500 |
| system.cpu2.icache.overall_miss_latency::total 12745500 |
| system.cpu2.icache.ReadReq_accesses::cpu2.inst 30662 |
| system.cpu2.icache.ReadReq_accesses::total 30662 |
| system.cpu2.icache.demand_accesses::cpu2.inst 30662 |
| system.cpu2.icache.demand_accesses::total 30662 |
| system.cpu2.icache.overall_accesses::cpu2.inst 30662 |
| system.cpu2.icache.overall_accesses::total 30662 |
| system.cpu2.icache.ReadReq_miss_rate::cpu2.inst 0.026221 |
| system.cpu2.icache.ReadReq_miss_rate::total 0.026221 |
| system.cpu2.icache.demand_miss_rate::cpu2.inst 0.026221 |
| system.cpu2.icache.demand_miss_rate::total 0.026221 |
| system.cpu2.icache.overall_miss_rate::cpu2.inst 0.026221 |
| system.cpu2.icache.overall_miss_rate::total 0.026221 |
| system.cpu2.icache.ReadReq_avg_miss_latency::cpu2.inst 15852.611940 |
| system.cpu2.icache.ReadReq_avg_miss_latency::total 15852.611940 |
| system.cpu2.icache.demand_avg_miss_latency::cpu2.inst 15852.611940 |
| system.cpu2.icache.demand_avg_miss_latency::total 15852.611940 |
| system.cpu2.icache.overall_avg_miss_latency::cpu2.inst 15852.611940 |
| system.cpu2.icache.overall_avg_miss_latency::total 15852.611940 |
| system.cpu2.icache.blocked_cycles::no_mshrs 39 |
| system.cpu2.icache.blocked_cycles::no_targets 0 |
| system.cpu2.icache.blocked::no_mshrs 2 |
| system.cpu2.icache.blocked::no_targets 0 |
| system.cpu2.icache.avg_blocked_cycles::no_mshrs 19.500000 |
| system.cpu2.icache.avg_blocked_cycles::no_targets nan |
| system.cpu2.icache.writebacks::writebacks 533 |
| system.cpu2.icache.writebacks::total 533 |
| system.cpu2.icache.ReadReq_mshr_hits::cpu2.inst 136 |
| system.cpu2.icache.ReadReq_mshr_hits::total 136 |
| system.cpu2.icache.demand_mshr_hits::cpu2.inst 136 |
| system.cpu2.icache.demand_mshr_hits::total 136 |
| system.cpu2.icache.overall_mshr_hits::cpu2.inst 136 |
| system.cpu2.icache.overall_mshr_hits::total 136 |
| system.cpu2.icache.ReadReq_mshr_misses::cpu2.inst 668 |
| system.cpu2.icache.ReadReq_mshr_misses::total 668 |
| system.cpu2.icache.demand_mshr_misses::cpu2.inst 668 |
| system.cpu2.icache.demand_mshr_misses::total 668 |
| system.cpu2.icache.overall_mshr_misses::cpu2.inst 668 |
| system.cpu2.icache.overall_mshr_misses::total 668 |
| system.cpu2.icache.ReadReq_mshr_miss_latency::cpu2.inst 10698000 |
| system.cpu2.icache.ReadReq_mshr_miss_latency::total 10698000 |
| system.cpu2.icache.demand_mshr_miss_latency::cpu2.inst 10698000 |
| system.cpu2.icache.demand_mshr_miss_latency::total 10698000 |
| system.cpu2.icache.overall_mshr_miss_latency::cpu2.inst 10698000 |
| system.cpu2.icache.overall_mshr_miss_latency::total 10698000 |
| system.cpu2.icache.ReadReq_mshr_miss_rate::cpu2.inst 0.021786 |
| system.cpu2.icache.ReadReq_mshr_miss_rate::total 0.021786 |
| system.cpu2.icache.demand_mshr_miss_rate::cpu2.inst 0.021786 |
| system.cpu2.icache.demand_mshr_miss_rate::total 0.021786 |
| system.cpu2.icache.overall_mshr_miss_rate::cpu2.inst 0.021786 |
| system.cpu2.icache.overall_mshr_miss_rate::total 0.021786 |
| system.cpu2.icache.ReadReq_avg_mshr_miss_latency::cpu2.inst 16014.970060 |
| system.cpu2.icache.ReadReq_avg_mshr_miss_latency::total 16014.970060 |
| system.cpu2.icache.demand_avg_mshr_miss_latency::cpu2.inst 16014.970060 |
| system.cpu2.icache.demand_avg_mshr_miss_latency::total 16014.970060 |
| system.cpu2.icache.overall_avg_mshr_miss_latency::cpu2.inst 16014.970060 |
| system.cpu2.icache.overall_avg_mshr_miss_latency::total 16014.970060 |
| system.cpu3.branchPred.lookups 72293 |
| system.cpu3.branchPred.condPredicted 64508 |
| system.cpu3.branchPred.condIncorrect 2352 |
| system.cpu3.branchPred.BTBLookups 63427 |
| system.cpu3.branchPred.BTBHits 0 |
| system.cpu3.branchPred.BTBCorrect 0 |
| system.cpu3.branchPred.BTBHitPct 0.000000 |
| system.cpu3.branchPred.usedRAS 2060 |
| system.cpu3.branchPred.RASInCorrect 231 |
| system.cpu3.branchPred.indirectLookups 63427 |
| system.cpu3.branchPred.indirectHits 53739 |
| system.cpu3.branchPred.indirectMisses 9688 |
| system.cpu3.branchPredindirectMispredicted 1247 |
| system.cpu3.pwrStateResidencyTicks::ON 126524000 |
| system.cpu3.numCycles 193192 |
| system.cpu3.numWorkItemsStarted 0 |
| system.cpu3.numWorkItemsCompleted 0 |
| system.cpu3.fetch.icacheStallCycles 35761 |
| system.cpu3.fetch.Insts 398740 |
| system.cpu3.fetch.Branches 72293 |
| system.cpu3.fetch.predictedBranches 55799 |
| system.cpu3.fetch.Cycles 151769 |
| system.cpu3.fetch.SquashCycles 4859 |
| system.cpu3.fetch.MiscStallCycles 3 |
| system.cpu3.fetch.NoActiveThreadStallCycles 10 |
| system.cpu3.fetch.PendingTrapStallCycles 1574 |
| system.cpu3.fetch.CacheLines 24631 |
| system.cpu3.fetch.IcacheSquashes 962 |
| system.cpu3.fetch.rateDist::samples 191546 |
| system.cpu3.fetch.rateDist::mean 2.081693 |
| system.cpu3.fetch.rateDist::stdev 2.372350 |
| system.cpu3.fetch.rateDist::underflows 0 0.00% 0.00% |
| system.cpu3.fetch.rateDist::0 61472 32.09% 32.09% |
| system.cpu3.fetch.rateDist::1 63433 33.12% 65.21% |
| system.cpu3.fetch.rateDist::2 6639 3.47% 68.67% |
| system.cpu3.fetch.rateDist::3 3404 1.78% 70.45% |
| system.cpu3.fetch.rateDist::4 665 0.35% 70.80% |
| system.cpu3.fetch.rateDist::5 44919 23.45% 94.25% |
| system.cpu3.fetch.rateDist::6 1096 0.57% 94.82% |
| system.cpu3.fetch.rateDist::7 1358 0.71% 95.53% |
| system.cpu3.fetch.rateDist::8 8560 4.47% 100.00% |
| system.cpu3.fetch.rateDist::overflows 0 0.00% 100.00% |
| system.cpu3.fetch.rateDist::min_value 0 |
| system.cpu3.fetch.rateDist::max_value 8 |
| system.cpu3.fetch.rateDist::total 191546 |
| system.cpu3.fetch.branchRate 0.374203 |
| system.cpu3.fetch.rate 2.063957 |
| system.cpu3.decode.IdleCycles 22177 |
| system.cpu3.decode.BlockedCycles 57153 |
| system.cpu3.decode.RunCycles 106023 |
| system.cpu3.decode.UnblockCycles 3754 |
| system.cpu3.decode.SquashCycles 2429 |
| system.cpu3.decode.DecodedInsts 367896 |
| system.cpu3.rename.SquashCycles 2429 |
| system.cpu3.rename.IdleCycles 23211 |
| system.cpu3.rename.BlockCycles 26609 |
| system.cpu3.rename.serializeStallCycles 13121 |
| system.cpu3.rename.RunCycles 106749 |
| system.cpu3.rename.UnblockCycles 19417 |
| system.cpu3.rename.RenamedInsts 361084 |
| system.cpu3.rename.IQFullEvents 16689 |
| system.cpu3.rename.LQFullEvents 17 |
| system.cpu3.rename.RenamedOperands 253671 |
| system.cpu3.rename.RenameLookups 696424 |
| system.cpu3.rename.int_rename_lookups 539785 |
| system.cpu3.rename.fp_rename_lookups 26 |
| system.cpu3.rename.CommittedMaps 225321 |
| system.cpu3.rename.UndoneMaps 28350 |
| system.cpu3.rename.serializingInsts 1632 |
| system.cpu3.rename.tempSerializingInsts 1767 |
| system.cpu3.rename.skidInsts 25027 |
| system.cpu3.memDep0.insertedLoads 102074 |
| system.cpu3.memDep0.insertedStores 49198 |
| system.cpu3.memDep0.conflictingLoads 48321 |
| system.cpu3.memDep0.conflictingStores 42853 |
| system.cpu3.iq.iqInstsAdded 296921 |
| system.cpu3.iq.iqNonSpecInstsAdded 6960 |
| system.cpu3.iq.iqInstsIssued 296157 |
| system.cpu3.iq.iqSquashedInstsIssued 99 |
| system.cpu3.iq.iqSquashedInstsExamined 24377 |
| system.cpu3.iq.iqSquashedOperandsExamined 19466 |
| system.cpu3.iq.iqSquashedNonSpecRemoved 1109 |
| system.cpu3.iq.issued_per_cycle::samples 191546 |
| system.cpu3.iq.issued_per_cycle::mean 1.546140 |
| system.cpu3.iq.issued_per_cycle::stdev 1.378862 |
| system.cpu3.iq.issued_per_cycle::underflows 0 0.00% 0.00% |
| system.cpu3.iq.issued_per_cycle::0 66138 34.53% 34.53% |
| system.cpu3.iq.issued_per_cycle::1 22907 11.96% 46.49% |
| system.cpu3.iq.issued_per_cycle::2 47792 24.95% 71.44% |
| system.cpu3.iq.issued_per_cycle::3 47510 24.80% 96.24% |
| system.cpu3.iq.issued_per_cycle::4 3644 1.90% 98.14% |
| system.cpu3.iq.issued_per_cycle::5 1780 0.93% 99.07% |
| system.cpu3.iq.issued_per_cycle::6 1054 0.55% 99.62% |
| system.cpu3.iq.issued_per_cycle::7 432 0.23% 99.85% |
| system.cpu3.iq.issued_per_cycle::8 289 0.15% 100.00% |
| system.cpu3.iq.issued_per_cycle::overflows 0 0.00% 100.00% |
| system.cpu3.iq.issued_per_cycle::min_value 0 |
| system.cpu3.iq.issued_per_cycle::max_value 8 |
| system.cpu3.iq.issued_per_cycle::total 191546 |
| system.cpu3.iq.fu_full::No_OpClass 0 0.00% 0.00% |
| system.cpu3.iq.fu_full::IntAlu 185 40.13% 40.13% |
| system.cpu3.iq.fu_full::IntMult 0 0.00% 40.13% |
| system.cpu3.iq.fu_full::IntDiv 0 0.00% 40.13% |
| system.cpu3.iq.fu_full::FloatAdd 0 0.00% 40.13% |
| system.cpu3.iq.fu_full::FloatCmp 0 0.00% 40.13% |
| system.cpu3.iq.fu_full::FloatCvt 0 0.00% 40.13% |
| system.cpu3.iq.fu_full::FloatMult 0 0.00% 40.13% |
| system.cpu3.iq.fu_full::FloatMultAcc 0 0.00% 40.13% |
| system.cpu3.iq.fu_full::FloatDiv 0 0.00% 40.13% |
| system.cpu3.iq.fu_full::FloatMisc 0 0.00% 40.13% |
| system.cpu3.iq.fu_full::FloatSqrt 0 0.00% 40.13% |
| system.cpu3.iq.fu_full::SimdAdd 0 0.00% 40.13% |
| system.cpu3.iq.fu_full::SimdAddAcc 0 0.00% 40.13% |
| system.cpu3.iq.fu_full::SimdAlu 0 0.00% 40.13% |
| system.cpu3.iq.fu_full::SimdCmp 0 0.00% 40.13% |
| system.cpu3.iq.fu_full::SimdCvt 0 0.00% 40.13% |
| system.cpu3.iq.fu_full::SimdMisc 0 0.00% 40.13% |
| system.cpu3.iq.fu_full::SimdMult 0 0.00% 40.13% |
| system.cpu3.iq.fu_full::SimdMultAcc 0 0.00% 40.13% |
| system.cpu3.iq.fu_full::SimdShift 0 0.00% 40.13% |
| system.cpu3.iq.fu_full::SimdShiftAcc 0 0.00% 40.13% |
| system.cpu3.iq.fu_full::SimdSqrt 0 0.00% 40.13% |
| system.cpu3.iq.fu_full::SimdFloatAdd 0 0.00% 40.13% |
| system.cpu3.iq.fu_full::SimdFloatAlu 0 0.00% 40.13% |
| system.cpu3.iq.fu_full::SimdFloatCmp 0 0.00% 40.13% |
| system.cpu3.iq.fu_full::SimdFloatCvt 0 0.00% 40.13% |
| system.cpu3.iq.fu_full::SimdFloatDiv 0 0.00% 40.13% |
| system.cpu3.iq.fu_full::SimdFloatMisc 0 0.00% 40.13% |
| system.cpu3.iq.fu_full::SimdFloatMult 0 0.00% 40.13% |
| system.cpu3.iq.fu_full::SimdFloatMultAcc 0 0.00% 40.13% |
| system.cpu3.iq.fu_full::SimdFloatSqrt 0 0.00% 40.13% |
| system.cpu3.iq.fu_full::MemRead 47 10.20% 50.33% |
| system.cpu3.iq.fu_full::MemWrite 229 49.67% 100.00% |
| system.cpu3.iq.fu_full::FloatMemRead 0 0.00% 100.00% |
| system.cpu3.iq.fu_full::FloatMemWrite 0 0.00% 100.00% |
| system.cpu3.iq.fu_full::IprAccess 0 0.00% 100.00% |
| system.cpu3.iq.fu_full::InstPrefetch 0 0.00% 100.00% |
| system.cpu3.iq.FU_type_0::No_OpClass 0 0.00% 0.00% |
| system.cpu3.iq.FU_type_0::IntAlu 141800 47.88% 47.88% |
| system.cpu3.iq.FU_type_0::IntMult 0 0.00% 47.88% |
| system.cpu3.iq.FU_type_0::IntDiv 0 0.00% 47.88% |
| system.cpu3.iq.FU_type_0::FloatAdd 0 0.00% 47.88% |
| system.cpu3.iq.FU_type_0::FloatCmp 0 0.00% 47.88% |
| system.cpu3.iq.FU_type_0::FloatCvt 0 0.00% 47.88% |
| system.cpu3.iq.FU_type_0::FloatMult 0 0.00% 47.88% |
| system.cpu3.iq.FU_type_0::FloatMultAcc 0 0.00% 47.88% |
| system.cpu3.iq.FU_type_0::FloatDiv 0 0.00% 47.88% |
| system.cpu3.iq.FU_type_0::FloatMisc 0 0.00% 47.88% |
| system.cpu3.iq.FU_type_0::FloatSqrt 0 0.00% 47.88% |
| system.cpu3.iq.FU_type_0::SimdAdd 0 0.00% 47.88% |
| system.cpu3.iq.FU_type_0::SimdAddAcc 0 0.00% 47.88% |
| system.cpu3.iq.FU_type_0::SimdAlu 0 0.00% 47.88% |
| system.cpu3.iq.FU_type_0::SimdCmp 0 0.00% 47.88% |
| system.cpu3.iq.FU_type_0::SimdCvt 0 0.00% 47.88% |
| system.cpu3.iq.FU_type_0::SimdMisc 0 0.00% 47.88% |
| system.cpu3.iq.FU_type_0::SimdMult 0 0.00% 47.88% |
| system.cpu3.iq.FU_type_0::SimdMultAcc 0 0.00% 47.88% |
| system.cpu3.iq.FU_type_0::SimdShift 0 0.00% 47.88% |
| system.cpu3.iq.FU_type_0::SimdShiftAcc 0 0.00% 47.88% |
| system.cpu3.iq.FU_type_0::SimdSqrt 0 0.00% 47.88% |
| system.cpu3.iq.FU_type_0::SimdFloatAdd 0 0.00% 47.88% |
| system.cpu3.iq.FU_type_0::SimdFloatAlu 0 0.00% 47.88% |
| system.cpu3.iq.FU_type_0::SimdFloatCmp 0 0.00% 47.88% |
| system.cpu3.iq.FU_type_0::SimdFloatCvt 0 0.00% 47.88% |
| system.cpu3.iq.FU_type_0::SimdFloatDiv 0 0.00% 47.88% |
| system.cpu3.iq.FU_type_0::SimdFloatMisc 0 0.00% 47.88% |
| system.cpu3.iq.FU_type_0::SimdFloatMult 0 0.00% 47.88% |
| system.cpu3.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 47.88% |
| system.cpu3.iq.FU_type_0::SimdFloatSqrt 0 0.00% 47.88% |
| system.cpu3.iq.FU_type_0::MemRead 106215 35.86% 83.74% |
| system.cpu3.iq.FU_type_0::MemWrite 48142 16.26% 100.00% |
| system.cpu3.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% |
| system.cpu3.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% |
| system.cpu3.iq.FU_type_0::IprAccess 0 0.00% 100.00% |
| system.cpu3.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% |
| system.cpu3.iq.FU_type_0::total 296157 |
| system.cpu3.iq.rate 1.532967 |
| system.cpu3.iq.fu_busy_cnt 461 |
| system.cpu3.iq.fu_busy_rate 0.001557 |
| system.cpu3.iq.int_inst_queue_reads 784420 |
| system.cpu3.iq.int_inst_queue_writes 328242 |
| system.cpu3.iq.int_inst_queue_wakeup_accesses 292189 |
| system.cpu3.iq.fp_inst_queue_reads 0 |
| system.cpu3.iq.fp_inst_queue_writes 52 |
| system.cpu3.iq.fp_inst_queue_wakeup_accesses 0 |
| system.cpu3.iq.int_alu_accesses 296618 |
| system.cpu3.iq.fp_alu_accesses 0 |
| system.cpu3.iew.lsq.thread0.forwLoads 42744 |
| system.cpu3.iew.lsq.thread0.invAddrLoads 0 |
| system.cpu3.iew.lsq.thread0.squashedLoads 4403 |
| system.cpu3.iew.lsq.thread0.ignoredResponses 29 |
| system.cpu3.iew.lsq.thread0.memOrderViolation 36 |
| system.cpu3.iew.lsq.thread0.squashedStores 2674 |
| system.cpu3.iew.lsq.thread0.invAddrSwpfs 0 |
| system.cpu3.iew.lsq.thread0.blockedLoads 0 |
| system.cpu3.iew.lsq.thread0.rescheduledLoads 0 |
| system.cpu3.iew.lsq.thread0.cacheBlocked 0 |
| system.cpu3.iew.iewIdleCycles 0 |
| system.cpu3.iew.iewSquashCycles 2429 |
| system.cpu3.iew.iewBlockCycles 7527 |
| system.cpu3.iew.iewUnblockCycles 48 |
| system.cpu3.iew.iewDispatchedInsts 353355 |
| system.cpu3.iew.iewDispSquashedInsts 397 |
| system.cpu3.iew.iewDispLoadInsts 102074 |
| system.cpu3.iew.iewDispStoreInsts 49198 |
| system.cpu3.iew.iewDispNonSpecInsts 1516 |
| system.cpu3.iew.iewIQFullEvents 34 |
| system.cpu3.iew.iewLSQFullEvents 0 |
| system.cpu3.iew.memOrderViolationEvents 36 |
| system.cpu3.iew.predictedTakenIncorrect 456 |
| system.cpu3.iew.predictedNotTakenIncorrect 2533 |
| system.cpu3.iew.branchMispredicts 2989 |
| system.cpu3.iew.iewExecutedInsts 293543 |
| system.cpu3.iew.iewExecLoadInsts 100466 |
| system.cpu3.iew.iewExecSquashedInsts 2614 |
| system.cpu3.iew.exec_swp 0 |
| system.cpu3.iew.exec_nop 49474 |
| system.cpu3.iew.exec_refs 148308 |
| system.cpu3.iew.exec_branches 59826 |
| system.cpu3.iew.exec_stores 47842 |
| system.cpu3.iew.exec_rate 1.519437 |
| system.cpu3.iew.wb_sent 292703 |
| system.cpu3.iew.wb_count 292189 |
| system.cpu3.iew.wb_producers 166184 |
| system.cpu3.iew.wb_consumers 173731 |
| system.cpu3.iew.wb_rate 1.512428 |
| system.cpu3.iew.wb_fanout 0.956559 |
| system.cpu3.commit.commitSquashedInsts 25409 |
| system.cpu3.commit.commitNonSpecStalls 5851 |
| system.cpu3.commit.branchMispredicts 2352 |
| system.cpu3.commit.committed_per_cycle::samples 186670 |
| system.cpu3.commit.committed_per_cycle::mean 1.756683 |
| system.cpu3.commit.committed_per_cycle::stdev 2.084505 |
| system.cpu3.commit.committed_per_cycle::underflows 0 0.00% 0.00% |
| system.cpu3.commit.committed_per_cycle::0 71411 38.26% 38.26% |
| system.cpu3.commit.committed_per_cycle::1 56079 30.04% 68.30% |
| system.cpu3.commit.committed_per_cycle::2 5419 2.90% 71.20% |
| system.cpu3.commit.committed_per_cycle::3 6543 3.51% 74.71% |
| system.cpu3.commit.committed_per_cycle::4 1250 0.67% 75.37% |
| system.cpu3.commit.committed_per_cycle::5 42928 23.00% 98.37% |
| system.cpu3.commit.committed_per_cycle::6 773 0.41% 98.79% |
| system.cpu3.commit.committed_per_cycle::7 1040 0.56% 99.34% |
| system.cpu3.commit.committed_per_cycle::8 1227 0.66% 100.00% |
| system.cpu3.commit.committed_per_cycle::overflows 0 0.00% 100.00% |
| system.cpu3.commit.committed_per_cycle::min_value 0 |
| system.cpu3.commit.committed_per_cycle::max_value 8 |
| system.cpu3.commit.committed_per_cycle::total 186670 |
| system.cpu3.commit.committedInsts 327920 |
| system.cpu3.commit.committedOps 327920 |
| system.cpu3.commit.swp_count 0 |
| system.cpu3.commit.refs 144195 |
| system.cpu3.commit.loads 97671 |
| system.cpu3.commit.membars 5137 |
| system.cpu3.commit.branches 57626 |
| system.cpu3.commit.fp_insts 0 |
| system.cpu3.commit.int_insts 223941 |
| system.cpu3.commit.function_calls 322 |
| system.cpu3.commit.op_class_0::No_OpClass 48416 14.76% 14.76% |
| system.cpu3.commit.op_class_0::IntAlu 130172 39.70% 54.46% |
| system.cpu3.commit.op_class_0::IntMult 0 0.00% 54.46% |
| system.cpu3.commit.op_class_0::IntDiv 0 0.00% 54.46% |
| system.cpu3.commit.op_class_0::FloatAdd 0 0.00% 54.46% |
| system.cpu3.commit.op_class_0::FloatCmp 0 0.00% 54.46% |
| system.cpu3.commit.op_class_0::FloatCvt 0 0.00% 54.46% |
| system.cpu3.commit.op_class_0::FloatMult 0 0.00% 54.46% |
| system.cpu3.commit.op_class_0::FloatMultAcc 0 0.00% 54.46% |
| system.cpu3.commit.op_class_0::FloatDiv 0 0.00% 54.46% |
| system.cpu3.commit.op_class_0::FloatMisc 0 0.00% 54.46% |
| system.cpu3.commit.op_class_0::FloatSqrt 0 0.00% 54.46% |
| system.cpu3.commit.op_class_0::SimdAdd 0 0.00% 54.46% |
| system.cpu3.commit.op_class_0::SimdAddAcc 0 0.00% 54.46% |
| system.cpu3.commit.op_class_0::SimdAlu 0 0.00% 54.46% |
| system.cpu3.commit.op_class_0::SimdCmp 0 0.00% 54.46% |
| system.cpu3.commit.op_class_0::SimdCvt 0 0.00% 54.46% |
| system.cpu3.commit.op_class_0::SimdMisc 0 0.00% 54.46% |
| system.cpu3.commit.op_class_0::SimdMult 0 0.00% 54.46% |
| system.cpu3.commit.op_class_0::SimdMultAcc 0 0.00% 54.46% |
| system.cpu3.commit.op_class_0::SimdShift 0 0.00% 54.46% |
| system.cpu3.commit.op_class_0::SimdShiftAcc 0 0.00% 54.46% |
| system.cpu3.commit.op_class_0::SimdSqrt 0 0.00% 54.46% |
| system.cpu3.commit.op_class_0::SimdFloatAdd 0 0.00% 54.46% |
| system.cpu3.commit.op_class_0::SimdFloatAlu 0 0.00% 54.46% |
| system.cpu3.commit.op_class_0::SimdFloatCmp 0 0.00% 54.46% |
| system.cpu3.commit.op_class_0::SimdFloatCvt 0 0.00% 54.46% |
| system.cpu3.commit.op_class_0::SimdFloatDiv 0 0.00% 54.46% |
| system.cpu3.commit.op_class_0::SimdFloatMisc 0 0.00% 54.46% |
| system.cpu3.commit.op_class_0::SimdFloatMult 0 0.00% 54.46% |
| system.cpu3.commit.op_class_0::SimdFloatMultAcc 0 0.00% 54.46% |
| system.cpu3.commit.op_class_0::SimdFloatSqrt 0 0.00% 54.46% |
| system.cpu3.commit.op_class_0::MemRead 102808 31.35% 85.81% |
| system.cpu3.commit.op_class_0::MemWrite 46524 14.19% 100.00% |
| system.cpu3.commit.op_class_0::FloatMemRead 0 0.00% 100.00% |
| system.cpu3.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% |
| system.cpu3.commit.op_class_0::IprAccess 0 0.00% 100.00% |
| system.cpu3.commit.op_class_0::InstPrefetch 0 0.00% 100.00% |
| system.cpu3.commit.op_class_0::total 327920 |
| system.cpu3.commit.bw_lim_events 1227 |
| system.cpu3.rob.rob_reads 538186 |
| system.cpu3.rob.rob_writes 711575 |
| system.cpu3.timesIdled 229 |
| system.cpu3.idleCycles 1646 |
| system.cpu3.quiesceCycles 50195 |
| system.cpu3.committedInsts 274367 |
| system.cpu3.committedOps 274367 |
| system.cpu3.cpi 0.704137 |
| system.cpu3.cpi_total 0.704137 |
| system.cpu3.ipc 1.420178 |
| system.cpu3.ipc_total 1.420178 |
| system.cpu3.int_regfile_reads 509138 |
| system.cpu3.int_regfile_writes 236602 |
| system.cpu3.fp_regfile_writes 64 |
| system.cpu3.misc_regfile_reads 150205 |
| system.cpu3.misc_regfile_writes 652 |
| system.cpu3.dcache.tags.pwrStateResidencyTicks::UNDEFINED 126524000 |
| system.cpu3.dcache.tags.replacements 0 |
| system.cpu3.dcache.tags.tagsinuse 26.193054 |
| system.cpu3.dcache.tags.total_refs 53586 |
| system.cpu3.dcache.tags.sampled_refs 30 |
| system.cpu3.dcache.tags.avg_refs 1786.200000 |
| system.cpu3.dcache.tags.warmup_cycle 0 |
| system.cpu3.dcache.tags.occ_blocks::cpu3.data 26.193054 |
| system.cpu3.dcache.tags.occ_percent::cpu3.data 0.051158 |
| system.cpu3.dcache.tags.occ_percent::total 0.051158 |
| system.cpu3.dcache.tags.occ_task_id_blocks::1024 30 |
| system.cpu3.dcache.tags.age_task_id_blocks_1024::1 26 |
| system.cpu3.dcache.tags.age_task_id_blocks_1024::2 4 |
| system.cpu3.dcache.tags.occ_task_id_percent::1024 0.058594 |
| system.cpu3.dcache.tags.tag_accesses 417128 |
| system.cpu3.dcache.tags.data_accesses 417128 |
| system.cpu3.dcache.pwrStateResidencyTicks::UNDEFINED 126524000 |
| system.cpu3.dcache.ReadReq_hits::cpu3.data 57193 |
| system.cpu3.dcache.ReadReq_hits::total 57193 |
| system.cpu3.dcache.WriteReq_hits::cpu3.data 46316 |
| system.cpu3.dcache.WriteReq_hits::total 46316 |
| system.cpu3.dcache.SwapReq_hits::cpu3.data 12 |
| system.cpu3.dcache.SwapReq_hits::total 12 |
| system.cpu3.dcache.demand_hits::cpu3.data 103509 |
| system.cpu3.dcache.demand_hits::total 103509 |
| system.cpu3.dcache.overall_hits::cpu3.data 103509 |
| system.cpu3.dcache.overall_hits::total 103509 |
| system.cpu3.dcache.ReadReq_misses::cpu3.data 502 |
| system.cpu3.dcache.ReadReq_misses::total 502 |
| system.cpu3.dcache.WriteReq_misses::cpu3.data 140 |
| system.cpu3.dcache.WriteReq_misses::total 140 |
| system.cpu3.dcache.SwapReq_misses::cpu3.data 56 |
| system.cpu3.dcache.SwapReq_misses::total 56 |
| system.cpu3.dcache.demand_misses::cpu3.data 642 |
| system.cpu3.dcache.demand_misses::total 642 |
| system.cpu3.dcache.overall_misses::cpu3.data 642 |
| system.cpu3.dcache.overall_misses::total 642 |
| system.cpu3.dcache.ReadReq_miss_latency::cpu3.data 3817000 |
| system.cpu3.dcache.ReadReq_miss_latency::total 3817000 |
| system.cpu3.dcache.WriteReq_miss_latency::cpu3.data 2858000 |
| system.cpu3.dcache.WriteReq_miss_latency::total 2858000 |
| system.cpu3.dcache.SwapReq_miss_latency::cpu3.data 340000 |
| system.cpu3.dcache.SwapReq_miss_latency::total 340000 |
| system.cpu3.dcache.demand_miss_latency::cpu3.data 6675000 |
| system.cpu3.dcache.demand_miss_latency::total 6675000 |
| system.cpu3.dcache.overall_miss_latency::cpu3.data 6675000 |
| system.cpu3.dcache.overall_miss_latency::total 6675000 |
| system.cpu3.dcache.ReadReq_accesses::cpu3.data 57695 |
| system.cpu3.dcache.ReadReq_accesses::total 57695 |
| system.cpu3.dcache.WriteReq_accesses::cpu3.data 46456 |
| system.cpu3.dcache.WriteReq_accesses::total 46456 |
| system.cpu3.dcache.SwapReq_accesses::cpu3.data 68 |
| system.cpu3.dcache.SwapReq_accesses::total 68 |
| system.cpu3.dcache.demand_accesses::cpu3.data 104151 |
| system.cpu3.dcache.demand_accesses::total 104151 |
| system.cpu3.dcache.overall_accesses::cpu3.data 104151 |
| system.cpu3.dcache.overall_accesses::total 104151 |
| system.cpu3.dcache.ReadReq_miss_rate::cpu3.data 0.008701 |
| system.cpu3.dcache.ReadReq_miss_rate::total 0.008701 |
| system.cpu3.dcache.WriteReq_miss_rate::cpu3.data 0.003014 |
| system.cpu3.dcache.WriteReq_miss_rate::total 0.003014 |
| system.cpu3.dcache.SwapReq_miss_rate::cpu3.data 0.823529 |
| system.cpu3.dcache.SwapReq_miss_rate::total 0.823529 |
| system.cpu3.dcache.demand_miss_rate::cpu3.data 0.006164 |
| system.cpu3.dcache.demand_miss_rate::total 0.006164 |
| system.cpu3.dcache.overall_miss_rate::cpu3.data 0.006164 |
| system.cpu3.dcache.overall_miss_rate::total 0.006164 |
| system.cpu3.dcache.ReadReq_avg_miss_latency::cpu3.data 7603.585657 |
| system.cpu3.dcache.ReadReq_avg_miss_latency::total 7603.585657 |
| system.cpu3.dcache.WriteReq_avg_miss_latency::cpu3.data 20414.285714 |
| system.cpu3.dcache.WriteReq_avg_miss_latency::total 20414.285714 |
| system.cpu3.dcache.SwapReq_avg_miss_latency::cpu3.data 6071.428571 |
| system.cpu3.dcache.SwapReq_avg_miss_latency::total 6071.428571 |
| system.cpu3.dcache.demand_avg_miss_latency::cpu3.data 10397.196262 |
| system.cpu3.dcache.demand_avg_miss_latency::total 10397.196262 |
| system.cpu3.dcache.overall_avg_miss_latency::cpu3.data 10397.196262 |
| system.cpu3.dcache.overall_avg_miss_latency::total 10397.196262 |
| system.cpu3.dcache.blocked_cycles::no_mshrs 0 |
| system.cpu3.dcache.blocked_cycles::no_targets 0 |
| system.cpu3.dcache.blocked::no_mshrs 0 |
| system.cpu3.dcache.blocked::no_targets 0 |
| system.cpu3.dcache.avg_blocked_cycles::no_mshrs nan |
| system.cpu3.dcache.avg_blocked_cycles::no_targets nan |
| system.cpu3.dcache.ReadReq_mshr_hits::cpu3.data 340 |
| system.cpu3.dcache.ReadReq_mshr_hits::total 340 |
| system.cpu3.dcache.WriteReq_mshr_hits::cpu3.data 34 |
| system.cpu3.dcache.WriteReq_mshr_hits::total 34 |
| system.cpu3.dcache.demand_mshr_hits::cpu3.data 374 |
| system.cpu3.dcache.demand_mshr_hits::total 374 |
| system.cpu3.dcache.overall_mshr_hits::cpu3.data 374 |
| system.cpu3.dcache.overall_mshr_hits::total 374 |
| system.cpu3.dcache.ReadReq_mshr_misses::cpu3.data 162 |
| system.cpu3.dcache.ReadReq_mshr_misses::total 162 |
| system.cpu3.dcache.WriteReq_mshr_misses::cpu3.data 106 |
| system.cpu3.dcache.WriteReq_mshr_misses::total 106 |
| system.cpu3.dcache.SwapReq_mshr_misses::cpu3.data 56 |
| system.cpu3.dcache.SwapReq_mshr_misses::total 56 |
| system.cpu3.dcache.demand_mshr_misses::cpu3.data 268 |
| system.cpu3.dcache.demand_mshr_misses::total 268 |
| system.cpu3.dcache.overall_mshr_misses::cpu3.data 268 |
| system.cpu3.dcache.overall_mshr_misses::total 268 |
| system.cpu3.dcache.ReadReq_mshr_miss_latency::cpu3.data 1182500 |
| system.cpu3.dcache.ReadReq_mshr_miss_latency::total 1182500 |
| system.cpu3.dcache.WriteReq_mshr_miss_latency::cpu3.data 1396000 |
| system.cpu3.dcache.WriteReq_mshr_miss_latency::total 1396000 |
| system.cpu3.dcache.SwapReq_mshr_miss_latency::cpu3.data 284000 |
| system.cpu3.dcache.SwapReq_mshr_miss_latency::total 284000 |
| system.cpu3.dcache.demand_mshr_miss_latency::cpu3.data 2578500 |
| system.cpu3.dcache.demand_mshr_miss_latency::total 2578500 |
| system.cpu3.dcache.overall_mshr_miss_latency::cpu3.data 2578500 |
| system.cpu3.dcache.overall_mshr_miss_latency::total 2578500 |
| system.cpu3.dcache.ReadReq_mshr_miss_rate::cpu3.data 0.002808 |
| system.cpu3.dcache.ReadReq_mshr_miss_rate::total 0.002808 |
| system.cpu3.dcache.WriteReq_mshr_miss_rate::cpu3.data 0.002282 |
| system.cpu3.dcache.WriteReq_mshr_miss_rate::total 0.002282 |
| system.cpu3.dcache.SwapReq_mshr_miss_rate::cpu3.data 0.823529 |
| system.cpu3.dcache.SwapReq_mshr_miss_rate::total 0.823529 |
| system.cpu3.dcache.demand_mshr_miss_rate::cpu3.data 0.002573 |
| system.cpu3.dcache.demand_mshr_miss_rate::total 0.002573 |
| system.cpu3.dcache.overall_mshr_miss_rate::cpu3.data 0.002573 |
| system.cpu3.dcache.overall_mshr_miss_rate::total 0.002573 |
| system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::cpu3.data 7299.382716 |
| system.cpu3.dcache.ReadReq_avg_mshr_miss_latency::total 7299.382716 |
| system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::cpu3.data 13169.811321 |
| system.cpu3.dcache.WriteReq_avg_mshr_miss_latency::total 13169.811321 |
| system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::cpu3.data 5071.428571 |
| system.cpu3.dcache.SwapReq_avg_mshr_miss_latency::total 5071.428571 |
| system.cpu3.dcache.demand_avg_mshr_miss_latency::cpu3.data 9621.268657 |
| system.cpu3.dcache.demand_avg_mshr_miss_latency::total 9621.268657 |
| system.cpu3.dcache.overall_avg_mshr_miss_latency::cpu3.data 9621.268657 |
| system.cpu3.dcache.overall_avg_mshr_miss_latency::total 9621.268657 |
| system.cpu3.icache.tags.pwrStateResidencyTicks::UNDEFINED 126524000 |
| system.cpu3.icache.tags.replacements 589 |
| system.cpu3.icache.tags.tagsinuse 95.413384 |
| system.cpu3.icache.tags.total_refs 23771 |
| system.cpu3.icache.tags.sampled_refs 723 |
| system.cpu3.icache.tags.avg_refs 32.878285 |
| system.cpu3.icache.tags.warmup_cycle 0 |
| system.cpu3.icache.tags.occ_blocks::cpu3.inst 95.413384 |
| system.cpu3.icache.tags.occ_percent::cpu3.inst 0.186354 |
| system.cpu3.icache.tags.occ_percent::total 0.186354 |
| system.cpu3.icache.tags.occ_task_id_blocks::1024 134 |
| system.cpu3.icache.tags.age_task_id_blocks_1024::0 2 |
| system.cpu3.icache.tags.age_task_id_blocks_1024::1 120 |
| system.cpu3.icache.tags.age_task_id_blocks_1024::2 12 |
| system.cpu3.icache.tags.occ_task_id_percent::1024 0.261719 |
| system.cpu3.icache.tags.tag_accesses 25354 |
| system.cpu3.icache.tags.data_accesses 25354 |
| system.cpu3.icache.pwrStateResidencyTicks::UNDEFINED 126524000 |
| system.cpu3.icache.ReadReq_hits::cpu3.inst 23771 |
| system.cpu3.icache.ReadReq_hits::total 23771 |
| system.cpu3.icache.demand_hits::cpu3.inst 23771 |
| system.cpu3.icache.demand_hits::total 23771 |
| system.cpu3.icache.overall_hits::cpu3.inst 23771 |
| system.cpu3.icache.overall_hits::total 23771 |
| system.cpu3.icache.ReadReq_misses::cpu3.inst 860 |
| system.cpu3.icache.ReadReq_misses::total 860 |
| system.cpu3.icache.demand_misses::cpu3.inst 860 |
| system.cpu3.icache.demand_misses::total 860 |
| system.cpu3.icache.overall_misses::cpu3.inst 860 |
| system.cpu3.icache.overall_misses::total 860 |
| system.cpu3.icache.ReadReq_miss_latency::cpu3.inst 13120500 |
| system.cpu3.icache.ReadReq_miss_latency::total 13120500 |
| system.cpu3.icache.demand_miss_latency::cpu3.inst 13120500 |
| system.cpu3.icache.demand_miss_latency::total 13120500 |
| system.cpu3.icache.overall_miss_latency::cpu3.inst 13120500 |
| system.cpu3.icache.overall_miss_latency::total 13120500 |
| system.cpu3.icache.ReadReq_accesses::cpu3.inst 24631 |
| system.cpu3.icache.ReadReq_accesses::total 24631 |
| system.cpu3.icache.demand_accesses::cpu3.inst 24631 |
| system.cpu3.icache.demand_accesses::total 24631 |
| system.cpu3.icache.overall_accesses::cpu3.inst 24631 |
| system.cpu3.icache.overall_accesses::total 24631 |
| system.cpu3.icache.ReadReq_miss_rate::cpu3.inst 0.034915 |
| system.cpu3.icache.ReadReq_miss_rate::total 0.034915 |
| system.cpu3.icache.demand_miss_rate::cpu3.inst 0.034915 |
| system.cpu3.icache.demand_miss_rate::total 0.034915 |
| system.cpu3.icache.overall_miss_rate::cpu3.inst 0.034915 |
| system.cpu3.icache.overall_miss_rate::total 0.034915 |
| system.cpu3.icache.ReadReq_avg_miss_latency::cpu3.inst 15256.395349 |
| system.cpu3.icache.ReadReq_avg_miss_latency::total 15256.395349 |
| system.cpu3.icache.demand_avg_miss_latency::cpu3.inst 15256.395349 |
| system.cpu3.icache.demand_avg_miss_latency::total 15256.395349 |
| system.cpu3.icache.overall_avg_miss_latency::cpu3.inst 15256.395349 |
| system.cpu3.icache.overall_avg_miss_latency::total 15256.395349 |
| system.cpu3.icache.blocked_cycles::no_mshrs 0 |
| system.cpu3.icache.blocked_cycles::no_targets 0 |
| system.cpu3.icache.blocked::no_mshrs 0 |
| system.cpu3.icache.blocked::no_targets 0 |
| system.cpu3.icache.avg_blocked_cycles::no_mshrs nan |
| system.cpu3.icache.avg_blocked_cycles::no_targets nan |
| system.cpu3.icache.writebacks::writebacks 589 |
| system.cpu3.icache.writebacks::total 589 |
| system.cpu3.icache.ReadReq_mshr_hits::cpu3.inst 137 |
| system.cpu3.icache.ReadReq_mshr_hits::total 137 |
| system.cpu3.icache.demand_mshr_hits::cpu3.inst 137 |
| system.cpu3.icache.demand_mshr_hits::total 137 |
| system.cpu3.icache.overall_mshr_hits::cpu3.inst 137 |
| system.cpu3.icache.overall_mshr_hits::total 137 |
| system.cpu3.icache.ReadReq_mshr_misses::cpu3.inst 723 |
| system.cpu3.icache.ReadReq_mshr_misses::total 723 |
| system.cpu3.icache.demand_mshr_misses::cpu3.inst 723 |
| system.cpu3.icache.demand_mshr_misses::total 723 |
| system.cpu3.icache.overall_mshr_misses::cpu3.inst 723 |
| system.cpu3.icache.overall_mshr_misses::total 723 |
| system.cpu3.icache.ReadReq_mshr_miss_latency::cpu3.inst 11427500 |
| system.cpu3.icache.ReadReq_mshr_miss_latency::total 11427500 |
| system.cpu3.icache.demand_mshr_miss_latency::cpu3.inst 11427500 |
| system.cpu3.icache.demand_mshr_miss_latency::total 11427500 |
| system.cpu3.icache.overall_mshr_miss_latency::cpu3.inst 11427500 |
| system.cpu3.icache.overall_mshr_miss_latency::total 11427500 |
| system.cpu3.icache.ReadReq_mshr_miss_rate::cpu3.inst 0.029353 |
| system.cpu3.icache.ReadReq_mshr_miss_rate::total 0.029353 |
| system.cpu3.icache.demand_mshr_miss_rate::cpu3.inst 0.029353 |
| system.cpu3.icache.demand_mshr_miss_rate::total 0.029353 |
| system.cpu3.icache.overall_mshr_miss_rate::cpu3.inst 0.029353 |
| system.cpu3.icache.overall_mshr_miss_rate::total 0.029353 |
| system.cpu3.icache.ReadReq_avg_mshr_miss_latency::cpu3.inst 15805.670816 |
| system.cpu3.icache.ReadReq_avg_mshr_miss_latency::total 15805.670816 |
| system.cpu3.icache.demand_avg_mshr_miss_latency::cpu3.inst 15805.670816 |
| system.cpu3.icache.demand_avg_mshr_miss_latency::total 15805.670816 |
| system.cpu3.icache.overall_avg_mshr_miss_latency::cpu3.inst 15805.670816 |
| system.cpu3.icache.overall_avg_mshr_miss_latency::total 15805.670816 |
| system.l2c.tags.pwrStateResidencyTicks::UNDEFINED 126524000 |
| system.l2c.tags.replacements 0 |
| system.l2c.tags.tagsinuse 563.321355 |
| system.l2c.tags.total_refs 3204 |
| system.l2c.tags.sampled_refs 706 |
| system.l2c.tags.avg_refs 4.538244 |
| system.l2c.tags.warmup_cycle 0 |
| system.l2c.tags.occ_blocks::cpu0.inst 296.928117 |
| system.l2c.tags.occ_blocks::cpu0.data 144.858983 |
| system.l2c.tags.occ_blocks::cpu1.inst 69.416277 |
| system.l2c.tags.occ_blocks::cpu1.data 15.941995 |
| system.l2c.tags.occ_blocks::cpu2.inst 8.217801 |
| system.l2c.tags.occ_blocks::cpu2.data 9.832103 |
| system.l2c.tags.occ_blocks::cpu3.inst 7.210411 |
| system.l2c.tags.occ_blocks::cpu3.data 10.915668 |
| system.l2c.tags.occ_percent::cpu0.inst 0.004531 |
| system.l2c.tags.occ_percent::cpu0.data 0.002210 |
| system.l2c.tags.occ_percent::cpu1.inst 0.001059 |
| system.l2c.tags.occ_percent::cpu1.data 0.000243 |
| system.l2c.tags.occ_percent::cpu2.inst 0.000125 |
| system.l2c.tags.occ_percent::cpu2.data 0.000150 |
| system.l2c.tags.occ_percent::cpu3.inst 0.000110 |
| system.l2c.tags.occ_percent::cpu3.data 0.000167 |
| system.l2c.tags.occ_percent::total 0.008596 |
| system.l2c.tags.occ_task_id_blocks::1024 706 |
| system.l2c.tags.age_task_id_blocks_1024::0 52 |
| system.l2c.tags.age_task_id_blocks_1024::1 137 |
| system.l2c.tags.age_task_id_blocks_1024::2 517 |
| system.l2c.tags.occ_task_id_percent::1024 0.010773 |
| system.l2c.tags.tag_accesses 32122 |
| system.l2c.tags.data_accesses 32122 |
| system.l2c.pwrStateResidencyTicks::UNDEFINED 126524000 |
| system.l2c.WritebackDirty_hits::writebacks 1 |
| system.l2c.WritebackDirty_hits::total 1 |
| system.l2c.WritebackClean_hits::writebacks 764 |
| system.l2c.WritebackClean_hits::total 764 |
| system.l2c.UpgradeReq_hits::cpu0.data 24 |
| system.l2c.UpgradeReq_hits::cpu1.data 24 |
| system.l2c.UpgradeReq_hits::cpu2.data 23 |
| system.l2c.UpgradeReq_hits::cpu3.data 21 |
| system.l2c.UpgradeReq_hits::total 92 |
| system.l2c.ReadCleanReq_hits::cpu0.inst 318 |
| system.l2c.ReadCleanReq_hits::cpu1.inst 642 |
| system.l2c.ReadCleanReq_hits::cpu2.inst 646 |
| system.l2c.ReadCleanReq_hits::cpu3.inst 708 |
| system.l2c.ReadCleanReq_hits::total 2314 |
| system.l2c.ReadSharedReq_hits::cpu0.data 5 |
| system.l2c.ReadSharedReq_hits::cpu1.data 5 |
| system.l2c.ReadSharedReq_hits::cpu2.data 11 |
| system.l2c.ReadSharedReq_hits::cpu3.data 11 |
| system.l2c.ReadSharedReq_hits::total 32 |
| system.l2c.demand_hits::cpu0.inst 318 |
| system.l2c.demand_hits::cpu0.data 5 |
| system.l2c.demand_hits::cpu1.inst 642 |
| system.l2c.demand_hits::cpu1.data 5 |
| system.l2c.demand_hits::cpu2.inst 646 |
| system.l2c.demand_hits::cpu2.data 11 |
| system.l2c.demand_hits::cpu3.inst 708 |
| system.l2c.demand_hits::cpu3.data 11 |
| system.l2c.demand_hits::total 2346 |
| system.l2c.overall_hits::cpu0.inst 318 |
| system.l2c.overall_hits::cpu0.data 5 |
| system.l2c.overall_hits::cpu1.inst 642 |
| system.l2c.overall_hits::cpu1.data 5 |
| system.l2c.overall_hits::cpu2.inst 646 |
| system.l2c.overall_hits::cpu2.data 11 |
| system.l2c.overall_hits::cpu3.inst 708 |
| system.l2c.overall_hits::cpu3.data 11 |
| system.l2c.overall_hits::total 2346 |
| system.l2c.ReadExReq_misses::cpu0.data 94 |
| system.l2c.ReadExReq_misses::cpu1.data 13 |
| system.l2c.ReadExReq_misses::cpu2.data 12 |
| system.l2c.ReadExReq_misses::cpu3.data 12 |
| system.l2c.ReadExReq_misses::total 131 |
| system.l2c.ReadCleanReq_misses::cpu0.inst 372 |
| system.l2c.ReadCleanReq_misses::cpu1.inst 95 |
| system.l2c.ReadCleanReq_misses::cpu2.inst 22 |
| system.l2c.ReadCleanReq_misses::cpu3.inst 15 |
| system.l2c.ReadCleanReq_misses::total 504 |
| system.l2c.ReadSharedReq_misses::cpu0.data 75 |
| system.l2c.ReadSharedReq_misses::cpu1.data 8 |
| system.l2c.ReadSharedReq_misses::cpu2.data 2 |
| system.l2c.ReadSharedReq_misses::cpu3.data 3 |
| system.l2c.ReadSharedReq_misses::total 88 |
| system.l2c.demand_misses::cpu0.inst 372 |
| system.l2c.demand_misses::cpu0.data 169 |
| system.l2c.demand_misses::cpu1.inst 95 |
| system.l2c.demand_misses::cpu1.data 21 |
| system.l2c.demand_misses::cpu2.inst 22 |
| system.l2c.demand_misses::cpu2.data 14 |
| system.l2c.demand_misses::cpu3.inst 15 |
| system.l2c.demand_misses::cpu3.data 15 |
| system.l2c.demand_misses::total 723 |
| system.l2c.overall_misses::cpu0.inst 372 |
| system.l2c.overall_misses::cpu0.data 169 |
| system.l2c.overall_misses::cpu1.inst 95 |
| system.l2c.overall_misses::cpu1.data 21 |
| system.l2c.overall_misses::cpu2.inst 22 |
| system.l2c.overall_misses::cpu2.data 14 |
| system.l2c.overall_misses::cpu3.inst 15 |
| system.l2c.overall_misses::cpu3.data 15 |
| system.l2c.overall_misses::total 723 |
| system.l2c.ReadExReq_miss_latency::cpu0.data 7911000 |
| system.l2c.ReadExReq_miss_latency::cpu1.data 1069500 |
| system.l2c.ReadExReq_miss_latency::cpu2.data 1214500 |
| system.l2c.ReadExReq_miss_latency::cpu3.data 955500 |
| system.l2c.ReadExReq_miss_latency::total 11150500 |
| system.l2c.ReadCleanReq_miss_latency::cpu0.inst 31119000 |
| system.l2c.ReadCleanReq_miss_latency::cpu1.inst 8458500 |
| system.l2c.ReadCleanReq_miss_latency::cpu2.inst 2352500 |
| system.l2c.ReadCleanReq_miss_latency::cpu3.inst 2347000 |
| system.l2c.ReadCleanReq_miss_latency::total 44277000 |
| system.l2c.ReadSharedReq_miss_latency::cpu0.data 6607000 |
| system.l2c.ReadSharedReq_miss_latency::cpu1.data 681000 |
| system.l2c.ReadSharedReq_miss_latency::cpu2.data 179500 |
| system.l2c.ReadSharedReq_miss_latency::cpu3.data 296500 |
| system.l2c.ReadSharedReq_miss_latency::total 7764000 |
| system.l2c.demand_miss_latency::cpu0.inst 31119000 |
| system.l2c.demand_miss_latency::cpu0.data 14518000 |
| system.l2c.demand_miss_latency::cpu1.inst 8458500 |
| system.l2c.demand_miss_latency::cpu1.data 1750500 |
| system.l2c.demand_miss_latency::cpu2.inst 2352500 |
| system.l2c.demand_miss_latency::cpu2.data 1394000 |
| system.l2c.demand_miss_latency::cpu3.inst 2347000 |
| system.l2c.demand_miss_latency::cpu3.data 1252000 |
| system.l2c.demand_miss_latency::total 63191500 |
| system.l2c.overall_miss_latency::cpu0.inst 31119000 |
| system.l2c.overall_miss_latency::cpu0.data 14518000 |
| system.l2c.overall_miss_latency::cpu1.inst 8458500 |
| system.l2c.overall_miss_latency::cpu1.data 1750500 |
| system.l2c.overall_miss_latency::cpu2.inst 2352500 |
| system.l2c.overall_miss_latency::cpu2.data 1394000 |
| system.l2c.overall_miss_latency::cpu3.inst 2347000 |
| system.l2c.overall_miss_latency::cpu3.data 1252000 |
| system.l2c.overall_miss_latency::total 63191500 |
| system.l2c.WritebackDirty_accesses::writebacks 1 |
| system.l2c.WritebackDirty_accesses::total 1 |
| system.l2c.WritebackClean_accesses::writebacks 764 |
| system.l2c.WritebackClean_accesses::total 764 |
| system.l2c.UpgradeReq_accesses::cpu0.data 24 |
| system.l2c.UpgradeReq_accesses::cpu1.data 24 |
| system.l2c.UpgradeReq_accesses::cpu2.data 23 |
| system.l2c.UpgradeReq_accesses::cpu3.data 21 |
| system.l2c.UpgradeReq_accesses::total 92 |
| system.l2c.ReadExReq_accesses::cpu0.data 94 |
| system.l2c.ReadExReq_accesses::cpu1.data 13 |
| system.l2c.ReadExReq_accesses::cpu2.data 12 |
| system.l2c.ReadExReq_accesses::cpu3.data 12 |
| system.l2c.ReadExReq_accesses::total 131 |
| system.l2c.ReadCleanReq_accesses::cpu0.inst 690 |
| system.l2c.ReadCleanReq_accesses::cpu1.inst 737 |
| system.l2c.ReadCleanReq_accesses::cpu2.inst 668 |
| system.l2c.ReadCleanReq_accesses::cpu3.inst 723 |
| system.l2c.ReadCleanReq_accesses::total 2818 |
| system.l2c.ReadSharedReq_accesses::cpu0.data 80 |
| system.l2c.ReadSharedReq_accesses::cpu1.data 13 |
| system.l2c.ReadSharedReq_accesses::cpu2.data 13 |
| system.l2c.ReadSharedReq_accesses::cpu3.data 14 |
| system.l2c.ReadSharedReq_accesses::total 120 |
| system.l2c.demand_accesses::cpu0.inst 690 |
| system.l2c.demand_accesses::cpu0.data 174 |
| system.l2c.demand_accesses::cpu1.inst 737 |
| system.l2c.demand_accesses::cpu1.data 26 |
| system.l2c.demand_accesses::cpu2.inst 668 |
| system.l2c.demand_accesses::cpu2.data 25 |
| system.l2c.demand_accesses::cpu3.inst 723 |
| system.l2c.demand_accesses::cpu3.data 26 |
| system.l2c.demand_accesses::total 3069 |
| system.l2c.overall_accesses::cpu0.inst 690 |
| system.l2c.overall_accesses::cpu0.data 174 |
| system.l2c.overall_accesses::cpu1.inst 737 |
| system.l2c.overall_accesses::cpu1.data 26 |
| system.l2c.overall_accesses::cpu2.inst 668 |
| system.l2c.overall_accesses::cpu2.data 25 |
| system.l2c.overall_accesses::cpu3.inst 723 |
| system.l2c.overall_accesses::cpu3.data 26 |
| system.l2c.overall_accesses::total 3069 |
| system.l2c.ReadExReq_miss_rate::cpu0.data 1 |
| system.l2c.ReadExReq_miss_rate::cpu1.data 1 |
| system.l2c.ReadExReq_miss_rate::cpu2.data 1 |
| system.l2c.ReadExReq_miss_rate::cpu3.data 1 |
| system.l2c.ReadExReq_miss_rate::total 1 |
| system.l2c.ReadCleanReq_miss_rate::cpu0.inst 0.539130 |
| system.l2c.ReadCleanReq_miss_rate::cpu1.inst 0.128901 |
| system.l2c.ReadCleanReq_miss_rate::cpu2.inst 0.032934 |
| system.l2c.ReadCleanReq_miss_rate::cpu3.inst 0.020747 |
| system.l2c.ReadCleanReq_miss_rate::total 0.178850 |
| system.l2c.ReadSharedReq_miss_rate::cpu0.data 0.937500 |
| system.l2c.ReadSharedReq_miss_rate::cpu1.data 0.615385 |
| system.l2c.ReadSharedReq_miss_rate::cpu2.data 0.153846 |
| system.l2c.ReadSharedReq_miss_rate::cpu3.data 0.214286 |
| system.l2c.ReadSharedReq_miss_rate::total 0.733333 |
| system.l2c.demand_miss_rate::cpu0.inst 0.539130 |
| system.l2c.demand_miss_rate::cpu0.data 0.971264 |
| system.l2c.demand_miss_rate::cpu1.inst 0.128901 |
| system.l2c.demand_miss_rate::cpu1.data 0.807692 |
| system.l2c.demand_miss_rate::cpu2.inst 0.032934 |
| system.l2c.demand_miss_rate::cpu2.data 0.560000 |
| system.l2c.demand_miss_rate::cpu3.inst 0.020747 |
| system.l2c.demand_miss_rate::cpu3.data 0.576923 |
| system.l2c.demand_miss_rate::total 0.235582 |
| system.l2c.overall_miss_rate::cpu0.inst 0.539130 |
| system.l2c.overall_miss_rate::cpu0.data 0.971264 |
| system.l2c.overall_miss_rate::cpu1.inst 0.128901 |
| system.l2c.overall_miss_rate::cpu1.data 0.807692 |
| system.l2c.overall_miss_rate::cpu2.inst 0.032934 |
| system.l2c.overall_miss_rate::cpu2.data 0.560000 |
| system.l2c.overall_miss_rate::cpu3.inst 0.020747 |
| system.l2c.overall_miss_rate::cpu3.data 0.576923 |
| system.l2c.overall_miss_rate::total 0.235582 |
| system.l2c.ReadExReq_avg_miss_latency::cpu0.data 84159.574468 |
| system.l2c.ReadExReq_avg_miss_latency::cpu1.data 82269.230769 |
| system.l2c.ReadExReq_avg_miss_latency::cpu2.data 101208.333333 |
| system.l2c.ReadExReq_avg_miss_latency::cpu3.data 79625 |
| system.l2c.ReadExReq_avg_miss_latency::total 85118.320611 |
| system.l2c.ReadCleanReq_avg_miss_latency::cpu0.inst 83653.225806 |
| system.l2c.ReadCleanReq_avg_miss_latency::cpu1.inst 89036.842105 |
| system.l2c.ReadCleanReq_avg_miss_latency::cpu2.inst 106931.818182 |
| system.l2c.ReadCleanReq_avg_miss_latency::cpu3.inst 156466.666667 |
| system.l2c.ReadCleanReq_avg_miss_latency::total 87851.190476 |
| system.l2c.ReadSharedReq_avg_miss_latency::cpu0.data 88093.333333 |
| system.l2c.ReadSharedReq_avg_miss_latency::cpu1.data 85125 |
| system.l2c.ReadSharedReq_avg_miss_latency::cpu2.data 89750 |
| system.l2c.ReadSharedReq_avg_miss_latency::cpu3.data 98833.333333 |
| system.l2c.ReadSharedReq_avg_miss_latency::total 88227.272727 |
| system.l2c.demand_avg_miss_latency::cpu0.inst 83653.225806 |
| system.l2c.demand_avg_miss_latency::cpu0.data 85905.325444 |
| system.l2c.demand_avg_miss_latency::cpu1.inst 89036.842105 |
| system.l2c.demand_avg_miss_latency::cpu1.data 83357.142857 |
| system.l2c.demand_avg_miss_latency::cpu2.inst 106931.818182 |
| system.l2c.demand_avg_miss_latency::cpu2.data 99571.428571 |
| system.l2c.demand_avg_miss_latency::cpu3.inst 156466.666667 |
| system.l2c.demand_avg_miss_latency::cpu3.data 83466.666667 |
| system.l2c.demand_avg_miss_latency::total 87401.798064 |
| system.l2c.overall_avg_miss_latency::cpu0.inst 83653.225806 |
| system.l2c.overall_avg_miss_latency::cpu0.data 85905.325444 |
| system.l2c.overall_avg_miss_latency::cpu1.inst 89036.842105 |
| system.l2c.overall_avg_miss_latency::cpu1.data 83357.142857 |
| system.l2c.overall_avg_miss_latency::cpu2.inst 106931.818182 |
| system.l2c.overall_avg_miss_latency::cpu2.data 99571.428571 |
| system.l2c.overall_avg_miss_latency::cpu3.inst 156466.666667 |
| system.l2c.overall_avg_miss_latency::cpu3.data 83466.666667 |
| system.l2c.overall_avg_miss_latency::total 87401.798064 |
| system.l2c.blocked_cycles::no_mshrs 0 |
| system.l2c.blocked_cycles::no_targets 0 |
| system.l2c.blocked::no_mshrs 0 |
| system.l2c.blocked::no_targets 0 |
| system.l2c.avg_blocked_cycles::no_mshrs nan |
| system.l2c.avg_blocked_cycles::no_targets nan |
| system.l2c.ReadCleanReq_mshr_hits::cpu0.inst 2 |
| system.l2c.ReadCleanReq_mshr_hits::cpu1.inst 3 |
| system.l2c.ReadCleanReq_mshr_hits::cpu2.inst 8 |
| system.l2c.ReadCleanReq_mshr_hits::cpu3.inst 3 |
| system.l2c.ReadCleanReq_mshr_hits::total 16 |
| system.l2c.demand_mshr_hits::cpu0.inst 2 |
| system.l2c.demand_mshr_hits::cpu1.inst 3 |
| system.l2c.demand_mshr_hits::cpu2.inst 8 |
| system.l2c.demand_mshr_hits::cpu3.inst 3 |
| system.l2c.demand_mshr_hits::total 16 |
| system.l2c.overall_mshr_hits::cpu0.inst 2 |
| system.l2c.overall_mshr_hits::cpu1.inst 3 |
| system.l2c.overall_mshr_hits::cpu2.inst 8 |
| system.l2c.overall_mshr_hits::cpu3.inst 3 |
| system.l2c.overall_mshr_hits::total 16 |
| system.l2c.ReadExReq_mshr_misses::cpu0.data 94 |
| system.l2c.ReadExReq_mshr_misses::cpu1.data 13 |
| system.l2c.ReadExReq_mshr_misses::cpu2.data 12 |
| system.l2c.ReadExReq_mshr_misses::cpu3.data 12 |
| system.l2c.ReadExReq_mshr_misses::total 131 |
| system.l2c.ReadCleanReq_mshr_misses::cpu0.inst 370 |
| system.l2c.ReadCleanReq_mshr_misses::cpu1.inst 92 |
| system.l2c.ReadCleanReq_mshr_misses::cpu2.inst 14 |
| system.l2c.ReadCleanReq_mshr_misses::cpu3.inst 12 |
| system.l2c.ReadCleanReq_mshr_misses::total 488 |
| system.l2c.ReadSharedReq_mshr_misses::cpu0.data 75 |
| system.l2c.ReadSharedReq_mshr_misses::cpu1.data 8 |
| system.l2c.ReadSharedReq_mshr_misses::cpu2.data 2 |
| system.l2c.ReadSharedReq_mshr_misses::cpu3.data 3 |
| system.l2c.ReadSharedReq_mshr_misses::total 88 |
| system.l2c.demand_mshr_misses::cpu0.inst 370 |
| system.l2c.demand_mshr_misses::cpu0.data 169 |
| system.l2c.demand_mshr_misses::cpu1.inst 92 |
| system.l2c.demand_mshr_misses::cpu1.data 21 |
| system.l2c.demand_mshr_misses::cpu2.inst 14 |
| system.l2c.demand_mshr_misses::cpu2.data 14 |
| system.l2c.demand_mshr_misses::cpu3.inst 12 |
| system.l2c.demand_mshr_misses::cpu3.data 15 |
| system.l2c.demand_mshr_misses::total 707 |
| system.l2c.overall_mshr_misses::cpu0.inst 370 |
| system.l2c.overall_mshr_misses::cpu0.data 169 |
| system.l2c.overall_mshr_misses::cpu1.inst 92 |
| system.l2c.overall_mshr_misses::cpu1.data 21 |
| system.l2c.overall_mshr_misses::cpu2.inst 14 |
| system.l2c.overall_mshr_misses::cpu2.data 14 |
| system.l2c.overall_mshr_misses::cpu3.inst 12 |
| system.l2c.overall_mshr_misses::cpu3.data 15 |
| system.l2c.overall_mshr_misses::total 707 |
| system.l2c.ReadExReq_mshr_miss_latency::cpu0.data 6971000 |
| system.l2c.ReadExReq_mshr_miss_latency::cpu1.data 939500 |
| system.l2c.ReadExReq_mshr_miss_latency::cpu2.data 1094500 |
| system.l2c.ReadExReq_mshr_miss_latency::cpu3.data 835500 |
| system.l2c.ReadExReq_mshr_miss_latency::total 9840500 |
| system.l2c.ReadCleanReq_mshr_miss_latency::cpu0.inst 27347000 |
| system.l2c.ReadCleanReq_mshr_miss_latency::cpu1.inst 7457000 |
| system.l2c.ReadCleanReq_mshr_miss_latency::cpu2.inst 1636500 |
| system.l2c.ReadCleanReq_mshr_miss_latency::cpu3.inst 2047500 |
| system.l2c.ReadCleanReq_mshr_miss_latency::total 38488000 |
| system.l2c.ReadSharedReq_mshr_miss_latency::cpu0.data 5857000 |
| system.l2c.ReadSharedReq_mshr_miss_latency::cpu1.data 601000 |
| system.l2c.ReadSharedReq_mshr_miss_latency::cpu2.data 159500 |
| system.l2c.ReadSharedReq_mshr_miss_latency::cpu3.data 266500 |
| system.l2c.ReadSharedReq_mshr_miss_latency::total 6884000 |
| system.l2c.demand_mshr_miss_latency::cpu0.inst 27347000 |
| system.l2c.demand_mshr_miss_latency::cpu0.data 12828000 |
| system.l2c.demand_mshr_miss_latency::cpu1.inst 7457000 |
| system.l2c.demand_mshr_miss_latency::cpu1.data 1540500 |
| system.l2c.demand_mshr_miss_latency::cpu2.inst 1636500 |
| system.l2c.demand_mshr_miss_latency::cpu2.data 1254000 |
| system.l2c.demand_mshr_miss_latency::cpu3.inst 2047500 |
| system.l2c.demand_mshr_miss_latency::cpu3.data 1102000 |
| system.l2c.demand_mshr_miss_latency::total 55212500 |
| system.l2c.overall_mshr_miss_latency::cpu0.inst 27347000 |
| system.l2c.overall_mshr_miss_latency::cpu0.data 12828000 |
| system.l2c.overall_mshr_miss_latency::cpu1.inst 7457000 |
| system.l2c.overall_mshr_miss_latency::cpu1.data 1540500 |
| system.l2c.overall_mshr_miss_latency::cpu2.inst 1636500 |
| system.l2c.overall_mshr_miss_latency::cpu2.data 1254000 |
| system.l2c.overall_mshr_miss_latency::cpu3.inst 2047500 |
| system.l2c.overall_mshr_miss_latency::cpu3.data 1102000 |
| system.l2c.overall_mshr_miss_latency::total 55212500 |
| system.l2c.ReadExReq_mshr_miss_rate::cpu0.data 1 |
| system.l2c.ReadExReq_mshr_miss_rate::cpu1.data 1 |
| system.l2c.ReadExReq_mshr_miss_rate::cpu2.data 1 |
| system.l2c.ReadExReq_mshr_miss_rate::cpu3.data 1 |
| system.l2c.ReadExReq_mshr_miss_rate::total 1 |
| system.l2c.ReadCleanReq_mshr_miss_rate::cpu0.inst 0.536232 |
| system.l2c.ReadCleanReq_mshr_miss_rate::cpu1.inst 0.124830 |
| system.l2c.ReadCleanReq_mshr_miss_rate::cpu2.inst 0.020958 |
| system.l2c.ReadCleanReq_mshr_miss_rate::cpu3.inst 0.016598 |
| system.l2c.ReadCleanReq_mshr_miss_rate::total 0.173172 |
| system.l2c.ReadSharedReq_mshr_miss_rate::cpu0.data 0.937500 |
| system.l2c.ReadSharedReq_mshr_miss_rate::cpu1.data 0.615385 |
| system.l2c.ReadSharedReq_mshr_miss_rate::cpu2.data 0.153846 |
| system.l2c.ReadSharedReq_mshr_miss_rate::cpu3.data 0.214286 |
| system.l2c.ReadSharedReq_mshr_miss_rate::total 0.733333 |
| system.l2c.demand_mshr_miss_rate::cpu0.inst 0.536232 |
| system.l2c.demand_mshr_miss_rate::cpu0.data 0.971264 |
| system.l2c.demand_mshr_miss_rate::cpu1.inst 0.124830 |
| system.l2c.demand_mshr_miss_rate::cpu1.data 0.807692 |
| system.l2c.demand_mshr_miss_rate::cpu2.inst 0.020958 |
| system.l2c.demand_mshr_miss_rate::cpu2.data 0.560000 |
| system.l2c.demand_mshr_miss_rate::cpu3.inst 0.016598 |
| system.l2c.demand_mshr_miss_rate::cpu3.data 0.576923 |
| system.l2c.demand_mshr_miss_rate::total 0.230368 |
| system.l2c.overall_mshr_miss_rate::cpu0.inst 0.536232 |
| system.l2c.overall_mshr_miss_rate::cpu0.data 0.971264 |
| system.l2c.overall_mshr_miss_rate::cpu1.inst 0.124830 |
| system.l2c.overall_mshr_miss_rate::cpu1.data 0.807692 |
| system.l2c.overall_mshr_miss_rate::cpu2.inst 0.020958 |
| system.l2c.overall_mshr_miss_rate::cpu2.data 0.560000 |
| system.l2c.overall_mshr_miss_rate::cpu3.inst 0.016598 |
| system.l2c.overall_mshr_miss_rate::cpu3.data 0.576923 |
| system.l2c.overall_mshr_miss_rate::total 0.230368 |
| system.l2c.ReadExReq_avg_mshr_miss_latency::cpu0.data 74159.574468 |
| system.l2c.ReadExReq_avg_mshr_miss_latency::cpu1.data 72269.230769 |
| system.l2c.ReadExReq_avg_mshr_miss_latency::cpu2.data 91208.333333 |
| system.l2c.ReadExReq_avg_mshr_miss_latency::cpu3.data 69625 |
| system.l2c.ReadExReq_avg_mshr_miss_latency::total 75118.320611 |
| system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu0.inst 73910.810811 |
| system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu1.inst 81054.347826 |
| system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu2.inst 116892.857143 |
| system.l2c.ReadCleanReq_avg_mshr_miss_latency::cpu3.inst 170625 |
| system.l2c.ReadCleanReq_avg_mshr_miss_latency::total 78868.852459 |
| system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu0.data 78093.333333 |
| system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu1.data 75125 |
| system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu2.data 79750 |
| system.l2c.ReadSharedReq_avg_mshr_miss_latency::cpu3.data 88833.333333 |
| system.l2c.ReadSharedReq_avg_mshr_miss_latency::total 78227.272727 |
| system.l2c.demand_avg_mshr_miss_latency::cpu0.inst 73910.810811 |
| system.l2c.demand_avg_mshr_miss_latency::cpu0.data 75905.325444 |
| system.l2c.demand_avg_mshr_miss_latency::cpu1.inst 81054.347826 |
| system.l2c.demand_avg_mshr_miss_latency::cpu1.data 73357.142857 |
| system.l2c.demand_avg_mshr_miss_latency::cpu2.inst 116892.857143 |
| system.l2c.demand_avg_mshr_miss_latency::cpu2.data 89571.428571 |
| system.l2c.demand_avg_mshr_miss_latency::cpu3.inst 170625 |
| system.l2c.demand_avg_mshr_miss_latency::cpu3.data 73466.666667 |
| system.l2c.demand_avg_mshr_miss_latency::total 78094.059406 |
| system.l2c.overall_avg_mshr_miss_latency::cpu0.inst 73910.810811 |
| system.l2c.overall_avg_mshr_miss_latency::cpu0.data 75905.325444 |
| system.l2c.overall_avg_mshr_miss_latency::cpu1.inst 81054.347826 |
| system.l2c.overall_avg_mshr_miss_latency::cpu1.data 73357.142857 |
| system.l2c.overall_avg_mshr_miss_latency::cpu2.inst 116892.857143 |
| system.l2c.overall_avg_mshr_miss_latency::cpu2.data 89571.428571 |
| system.l2c.overall_avg_mshr_miss_latency::cpu3.inst 170625 |
| system.l2c.overall_avg_mshr_miss_latency::cpu3.data 73466.666667 |
| system.l2c.overall_avg_mshr_miss_latency::total 78094.059406 |
| system.membus.snoop_filter.tot_requests 958 |
| system.membus.snoop_filter.hit_single_requests 252 |
| system.membus.snoop_filter.hit_multi_requests 0 |
| system.membus.snoop_filter.tot_snoops 0 |
| system.membus.snoop_filter.hit_single_snoops 0 |
| system.membus.snoop_filter.hit_multi_snoops 0 |
| system.membus.pwrStateResidencyTicks::UNDEFINED 126524000 |
| system.membus.trans_dist::ReadResp 575 |
| system.membus.trans_dist::UpgradeReq 198 |
| system.membus.trans_dist::ReadExReq 185 |
| system.membus.trans_dist::ReadExResp 131 |
| system.membus.trans_dist::ReadSharedReq 575 |
| system.membus.pkt_count_system.l2c.mem_side::system.physmem.port 1664 |
| system.membus.pkt_count::total 1664 |
| system.membus.pkt_size_system.l2c.mem_side::system.physmem.port 45184 |
| system.membus.pkt_size::total 45184 |
| system.membus.snoops 252 |
| system.membus.snoopTraffic 0 |
| system.membus.snoop_fanout::samples 958 |
| system.membus.snoop_fanout::mean 0 |
| system.membus.snoop_fanout::stdev 0 |
| system.membus.snoop_fanout::underflows 0 0.00% 0.00% |
| system.membus.snoop_fanout::0 958 100.00% 100.00% |
| system.membus.snoop_fanout::1 0 0.00% 100.00% |
| system.membus.snoop_fanout::overflows 0 0.00% 100.00% |
| system.membus.snoop_fanout::min_value 0 |
| system.membus.snoop_fanout::max_value 0 |
| system.membus.snoop_fanout::total 958 |
| system.membus.reqLayer0.occupancy 878500 |
| system.membus.reqLayer0.utilization 0.7 |
| system.membus.respLayer1.occupancy 3755250 |
| system.membus.respLayer1.utilization 3.0 |
| system.toL2Bus.snoop_filter.tot_requests 6322 |
| system.toL2Bus.snoop_filter.hit_single_requests 1691 |
| system.toL2Bus.snoop_filter.hit_multi_requests 3277 |
| system.toL2Bus.snoop_filter.tot_snoops 0 |
| system.toL2Bus.snoop_filter.hit_single_snoops 0 |
| system.toL2Bus.snoop_filter.hit_multi_snoops 0 |
| system.toL2Bus.pwrStateResidencyTicks::UNDEFINED 126524000 |
| system.toL2Bus.trans_dist::ReadResp 3512 |
| system.toL2Bus.trans_dist::ReadRespWithInvalidate 6 |
| system.toL2Bus.trans_dist::WritebackDirty 1 |
| system.toL2Bus.trans_dist::WritebackClean 2113 |
| system.toL2Bus.trans_dist::CleanEvict 1 |
| system.toL2Bus.trans_dist::UpgradeReq 290 |
| system.toL2Bus.trans_dist::UpgradeResp 290 |
| system.toL2Bus.trans_dist::ReadExReq 398 |
| system.toL2Bus.trans_dist::ReadExResp 398 |
| system.toL2Bus.trans_dist::ReadCleanReq 2818 |
| system.toL2Bus.trans_dist::ReadSharedReq 701 |
| system.toL2Bus.pkt_count_system.cpu0.icache.mem_side::system.l2c.cpu_side 1768 |
| system.toL2Bus.pkt_count_system.cpu0.dcache.mem_side::system.l2c.cpu_side 604 |
| system.toL2Bus.pkt_count_system.cpu1.icache.mem_side::system.l2c.cpu_side 2076 |
| system.toL2Bus.pkt_count_system.cpu1.dcache.mem_side::system.l2c.cpu_side 367 |
| system.toL2Bus.pkt_count_system.cpu2.icache.mem_side::system.l2c.cpu_side 1869 |
| system.toL2Bus.pkt_count_system.cpu2.dcache.mem_side::system.l2c.cpu_side 392 |
| system.toL2Bus.pkt_count_system.cpu3.icache.mem_side::system.l2c.cpu_side 2035 |
| system.toL2Bus.pkt_count_system.cpu3.dcache.mem_side::system.l2c.cpu_side 371 |
| system.toL2Bus.pkt_count::total 9482 |
| system.toL2Bus.pkt_size_system.cpu0.icache.mem_side::system.l2c.cpu_side 68992 |
| system.toL2Bus.pkt_size_system.cpu0.dcache.mem_side::system.l2c.cpu_side 11200 |
| system.toL2Bus.pkt_size_system.cpu1.icache.mem_side::system.l2c.cpu_side 85696 |
| system.toL2Bus.pkt_size_system.cpu1.dcache.mem_side::system.l2c.cpu_side 1664 |
| system.toL2Bus.pkt_size_system.cpu2.icache.mem_side::system.l2c.cpu_side 76864 |
| system.toL2Bus.pkt_size_system.cpu2.dcache.mem_side::system.l2c.cpu_side 1600 |
| system.toL2Bus.pkt_size_system.cpu3.icache.mem_side::system.l2c.cpu_side 83968 |
| system.toL2Bus.pkt_size_system.cpu3.dcache.mem_side::system.l2c.cpu_side 1664 |
| system.toL2Bus.pkt_size::total 331648 |
| system.toL2Bus.snoops 1046 |
| system.toL2Bus.snoopTraffic 54272 |
| system.toL2Bus.snoop_fanout::samples 4207 |
| system.toL2Bus.snoop_fanout::mean 1.309484 |
| system.toL2Bus.snoop_fanout::stdev 1.132145 |
| system.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% |
| system.toL2Bus.snoop_fanout::0 1354 32.18% 32.18% |
| system.toL2Bus.snoop_fanout::1 1089 25.89% 58.07% |
| system.toL2Bus.snoop_fanout::2 872 20.73% 78.80% |
| system.toL2Bus.snoop_fanout::3 892 21.20% 100.00% |
| system.toL2Bus.snoop_fanout::4 0 0.00% 100.00% |
| system.toL2Bus.snoop_fanout::5 0 0.00% 100.00% |
| system.toL2Bus.snoop_fanout::6 0 0.00% 100.00% |
| system.toL2Bus.snoop_fanout::7 0 0.00% 100.00% |
| system.toL2Bus.snoop_fanout::8 0 0.00% 100.00% |
| system.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% |
| system.toL2Bus.snoop_fanout::min_value 0 |
| system.toL2Bus.snoop_fanout::max_value 3 |
| system.toL2Bus.snoop_fanout::total 4207 |
| system.toL2Bus.reqLayer0.occupancy 5288473 |
| system.toL2Bus.reqLayer0.utilization 4.2 |
| system.toL2Bus.respLayer0.occupancy 1034498 |
| system.toL2Bus.respLayer0.utilization 0.8 |
| system.toL2Bus.respLayer1.occupancy 532490 |
| system.toL2Bus.respLayer1.utilization 0.4 |
| system.toL2Bus.respLayer2.occupancy 1106497 |
| system.toL2Bus.respLayer2.utilization 0.9 |
| system.toL2Bus.respLayer3.occupancy 422474 |
| system.toL2Bus.respLayer3.utilization 0.3 |
| system.toL2Bus.respLayer4.occupancy 1006490 |
| system.toL2Bus.respLayer4.utilization 0.8 |
| system.toL2Bus.respLayer5.occupancy 458964 |
| system.toL2Bus.respLayer5.utilization 0.4 |
| system.toL2Bus.respLayer6.occupancy 1085498 |
| system.toL2Bus.respLayer6.utilization 0.9 |
| system.toL2Bus.respLayer7.occupancy 428967 |
| system.toL2Bus.respLayer7.utilization 0.3 |
| |
| ---------- End Simulation Statistics ---------- |