commit 54e6625546fca51d54d79eb807c999d0756d8320
author Giacomo Travaglini <giacomo.travaglini@arm.com> Wed Aug 21 10:08:54 2019 +0100
committer Giacomo Travaglini <giacomo.travaglini@arm.com> Mon Sep 09 08:48:30 2019 +0000
tree 868219f3f8c4ee856f0fdaea1e62590a2e84c451
parent 5aa85f38cb15a8bfb76eaed074f892f99dbd1c68

dev-arm: Fix mapping between IGRPEN1_EL3 and IGRPEN1_EL1

Previous mapping was wrong because it was checking which security bits
it was accessing by using the inSecureState() function, whereas it
should have used the isSecureBelowEL3().  This patch is not making the
sostitution since it is optimizing the mapping furthermore by avoiding
updating both IGRPEN1_EL1 and  IGRPEN1_EL3 on writes.  The IGRPEN1_EL1
register is used as a storage, and any reads/writes to IGRPEN1_EL3 is
routed to that register.

Change-Id: Id318ec44e19d4f844e4e3410d74d0c4f89810811
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20632
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

src/dev/arm/gic_v3_cpu_interface.cc

diff --git a/src/dev/arm/gic_v3_cpu_interface.cc b/src/dev/arm/gic_v3_cpu_interface.cc
index 0cb0367..792337f 100644
--- a/src/dev/arm/gic_v3_cpu_interface.cc
+++ b/src/dev/arm/gic_v3_cpu_interface.cc
@@ -204,8 +204,17 @@
 
       // Interrupt Group 1 Enable register EL3
       case MISCREG_ICC_MGRPEN1:
-      case MISCREG_ICC_IGRPEN1_EL3:
+      case MISCREG_ICC_IGRPEN1_EL3: {
+          ICC_IGRPEN1_EL3 igrp_el3 = 0;
+          igrp_el3.EnableGrp1S = ((ICC_IGRPEN1_EL1)isa->readMiscRegNoEffect(
+              MISCREG_ICC_IGRPEN1_EL1_S)).Enable;
+
+          igrp_el3.EnableGrp1NS = ((ICC_IGRPEN1_EL1)isa->readMiscRegNoEffect(
+              MISCREG_ICC_IGRPEN1_EL1_NS)).Enable;
+
+          value = igrp_el3;
           break;
+      }
 
       // Running Priority Register
       case MISCREG_ICC_RPR:
@@ -1344,23 +1353,6 @@
               return setMiscReg(MISCREG_ICV_IGRPEN1_EL1, val);
           }
 
-          if (haveEL(EL3)) {
-              ICC_IGRPEN1_EL1 icc_igrpen1_el1 = val;
-              ICC_IGRPEN1_EL3 icc_igrpen1_el3 =
-                  isa->readMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL3);
-
-              if (inSecureState()) {
-                  // Enable is RW alias of ICC_IGRPEN1_EL3.EnableGrp1S
-                  icc_igrpen1_el3.EnableGrp1S = icc_igrpen1_el1.Enable;
-              } else {
-                  // Enable is RW alias of ICC_IGRPEN1_EL3.EnableGrp1NS
-                  icc_igrpen1_el3.EnableGrp1NS = icc_igrpen1_el1.Enable;
-              }
-
-              isa->setMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL3,
-                                      icc_igrpen1_el3);
-          }
-
           setBankedMiscReg(MISCREG_ICC_IGRPEN1_EL1, val);
           updateDistributor();
           return;
@@ -1381,19 +1373,12 @@
       case MISCREG_ICC_MGRPEN1:
       case MISCREG_ICC_IGRPEN1_EL3: {
           ICC_IGRPEN1_EL3 icc_igrpen1_el3 = val;
-          ICC_IGRPEN1_EL1 icc_igrpen1_el1 =
-              isa->readMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL1);
 
-          if (inSecureState()) {
-              // ICC_IGRPEN1_EL1.Enable is RW alias of EnableGrp1S
-              icc_igrpen1_el1.Enable = icc_igrpen1_el3.EnableGrp1S;
-          } else {
-              // ICC_IGRPEN1_EL1.Enable is RW alias of EnableGrp1NS
-              icc_igrpen1_el1.Enable = icc_igrpen1_el3.EnableGrp1NS;
-          }
-
-          isa->setMiscRegNoEffect(MISCREG_ICC_IGRPEN1_EL1, icc_igrpen1_el1);
-          break;
+          isa->setMiscRegNoEffect(
+              MISCREG_ICC_IGRPEN1_EL1_S, icc_igrpen1_el3.EnableGrp1S);
+          isa->setMiscRegNoEffect(
+              MISCREG_ICC_IGRPEN1_EL1_NS, icc_igrpen1_el3.EnableGrp1NS);
+          return;
       }
 
       // Software Generated Interrupt Group 0 Register