src/arch/riscv/SConscript

# -*- mode:python -*-

# Copyright (c) 2013 ARM Limited
# Copyright (c) 2014 Sven Karlsson
# Copyright (c) 2020 Barkhausen Institut
# Copyright (c) 2021 Huawei International
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#
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# to a hardware implementation of the functionality of the software
# licensed hereunder.  You may use the software subject to the license
# terms below provided that you ensure that this notice is replicated
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# Copyright (c) 2016 The University of Virginia
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# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
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# redistributions in binary form must reproduce the above copyright
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Import('*')

if env['TARGET_ISA'] == 'riscv':
    Source('decoder.cc')
    Source('faults.cc')
    Source('isa.cc')
    Source('locked_mem.cc')
    Source('process.cc')
    Source('pagetable.cc')
    Source('pagetable_walker.cc')
    Source('pma_checker.cc')
    Source('pmp.cc')
    Source('reg_abi.cc')
    Source('remote_gdb.cc')
    Source('tlb.cc')

    Source('linux/se_workload.cc')
    Source('linux/fs_workload.cc')

    Source('bare_metal/fs_workload.cc')

    SimObject('PMAChecker.py')
    SimObject('PMP.py')
    SimObject('RiscvFsWorkload.py')
    SimObject('RiscvInterrupts.py')
    SimObject('RiscvISA.py')
    SimObject('RiscvMMU.py')
    SimObject('RiscvSeWorkload.py')
    SimObject('RiscvTLB.py')

    DebugFlag('RiscvMisc')
    DebugFlag('TLBVerbose')
    DebugFlag('PMP')

    # Add in files generated by the ISA description.
    ISADesc('isa/main.isa')

    GdbXml('riscv.xml', 'gdb_xml_riscv_target')
    GdbXml('riscv-64bit-cpu.xml', 'gdb_xml_riscv_cpu')
    GdbXml('riscv-64bit-fpu.xml', 'gdb_xml_riscv_fpu')
    GdbXml('riscv-64bit-csr.xml', 'gdb_xml_riscv_csr')