src/arch/arm/isa/insts/div.isa

// -*- mode:c++ -*-

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// Authors: Gabe Black

let {{
    sdivCode = '''
    if (Op2_sw == 0) {
        Dest_sw = 0;
    } else if (Op1_sw == INT_MIN && Op2_sw == -1) {
        Dest_sw = INT_MIN;
    } else {
        Dest_sw = Op1_sw / Op2_sw;
    }
    '''
    sdivIop = InstObjParams("sdiv", "Sdiv", "RegRegRegOp",
                            { "code": sdivCode,
                              "predicate_test": predicateTest,
                              "op_class": "IntDivOp"}, [])
    header_output = RegRegRegOpDeclare.subst(sdivIop)
    decoder_output = RegRegRegOpConstructor.subst(sdivIop)
    exec_output = PredOpExecute.subst(sdivIop)

    udivCode = '''
    if (Op2_uw == 0) {
        Dest_uw = 0;
    } else {
        Dest_uw = Op1_uw / Op2_uw;
    }
    '''
    udivIop = InstObjParams("udiv", "Udiv", "RegRegRegOp",
                            { "code": udivCode,
                              "predicate_test": predicateTest,
                              "op_class": "IntDivOp"}, [])
    header_output += RegRegRegOpDeclare.subst(udivIop)
    decoder_output += RegRegRegOpConstructor.subst(udivIop)
    exec_output += PredOpExecute.subst(udivIop)
}};