mem-cache: Fix PIF prefetcher compilation error with NULL ISA
Referencing BaseCPU is causing a compilation error when using the NULL ISA.
This patch changes the reference to a SimObject, which fixes the problem.
Change-Id: I2530486cab65974f5b83e54a733c4b0e98730d26
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17731
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
diff --git a/src/mem/cache/prefetch/Prefetcher.py b/src/mem/cache/prefetch/Prefetcher.py
index 404a442..aaa1408 100644
--- a/src/mem/cache/prefetch/Prefetcher.py
+++ b/src/mem/cache/prefetch/Prefetcher.py
@@ -43,7 +43,6 @@
from m5.params import *
from m5.proxy import *
-from m5.objects.BaseCPU import BaseCPU
from m5.objects.ClockedObject import ClockedObject
from m5.objects.IndexingPolicies import *
from m5.objects.ReplacementPolicies import *
@@ -481,6 +480,6 @@
"Replacement policy of the index")
def listenFromProbeRetiredInstructions(self, simObj):
- if not isinstance(simObj, BaseCPU):
- raise TypeError("argument must be of BaseCPU type")
+ if not isinstance(simObj, SimObject):
+ raise TypeError("argument must be of SimObject type")
self.addEvent(HWPProbeEventRetiredInsts(self, simObj,"RetiredInstsPC"))
