| # Copyright (c) 2021 The Regents of the University of California |
| # All rights reserved. |
| # |
| # Redistribution and use in source and binary forms, with or without |
| # modification, are permitted provided that the following conditions are |
| # met: redistributions of source code must retain the above copyright |
| # notice, this list of conditions and the following disclaimer; |
| # redistributions in binary form must reproduce the above copyright |
| # notice, this list of conditions and the following disclaimer in the |
| # documentation and/or other materials provided with the distribution; |
| # neither the name of the copyright holders nor the names of its |
| # contributors may be used to endorse or promote products derived from |
| # this software without specific prior written permission. |
| # |
| # THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
| # "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
| # LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR |
| # A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT |
| # OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, |
| # SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT |
| # LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| # DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| # THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| |
| """ |
| |
| This script shows an example of running a full system Ubuntu boot simulation |
| using the gem5 library. This simulation boots Ubuntu 18.04 using 2 KVM CPU |
| cores. The simulation then switches to 2 Timing CPU cores before running an |
| echo statement. |
| |
| Usage |
| ----- |
| |
| ``` |
| scons build/X86/gem5.opt |
| ./build/X86/gem5.opt configs/example/gem5_library/x86-ubuntu-run-with-kvm.py |
| ``` |
| """ |
| |
| from gem5.utils.requires import requires |
| from gem5.components.boards.x86_board import X86Board |
| from gem5.components.memory.single_channel import SingleChannelDDR3_1600 |
| from gem5.components.processors.simple_switchable_processor import ( |
| SimpleSwitchableProcessor, |
| ) |
| from gem5.components.processors.cpu_types import CPUTypes |
| from gem5.isas import ISA |
| from gem5.coherence_protocol import CoherenceProtocol |
| from gem5.resources.resource import Resource |
| from gem5.simulate.simulator import Simulator |
| from gem5.simulate.exit_event import ExitEvent |
| |
| # This runs a check to ensure the gem5 binary is compiled to X86 and to the |
| # MESI Two Level coherence protocol. |
| requires( |
| isa_required=ISA.X86, |
| coherence_protocol_required=CoherenceProtocol.MESI_TWO_LEVEL, |
| kvm_required=True, |
| ) |
| |
| from gem5.components.cachehierarchies.ruby.\ |
| mesi_two_level_cache_hierarchy import ( |
| MESITwoLevelCacheHierarchy, |
| ) |
| |
| # Here we setup a MESI Two Level Cache Hierarchy. |
| cache_hierarchy = MESITwoLevelCacheHierarchy( |
| l1d_size="16kB", |
| l1d_assoc=8, |
| l1i_size="16kB", |
| l1i_assoc=8, |
| l2_size="256kB", |
| l2_assoc=16, |
| num_l2_banks=1, |
| ) |
| |
| # Setup the system memory. |
| memory = SingleChannelDDR3_1600(size="3GB") |
| |
| # Here we setup the processor. This is a special switchable processor in which |
| # a starting core type and a switch core type must be specified. Once a |
| # configuration is instantiated a user may call `processor.switch()` to switch |
| # from the starting core types to the switch core types. In this simulation |
| # we start with KVM cores to simulate the OS boot, then switch to the Timing |
| # cores for the command we wish to run after boot. |
| processor = SimpleSwitchableProcessor( |
| starting_core_type=CPUTypes.KVM, |
| switch_core_type=CPUTypes.TIMING, |
| num_cores=2, |
| ) |
| |
| # Here we setup the board. The X86Board allows for Full-System X86 simulations. |
| board = X86Board( |
| clk_freq="3GHz", |
| processor=processor, |
| memory=memory, |
| cache_hierarchy=cache_hierarchy, |
| ) |
| |
| # Here we set the Full System workload. |
| # The `set_kernel_disk_workload` function for the X86Board takes a kernel, a |
| # disk image, and, optionally, a command to run. |
| |
| # This is the command to run after the system has booted. The first `m5 exit` |
| # will stop the simulation so we can switch the CPU cores from KVM to timing |
| # and continue the simulation to run the echo command, sleep for a second, |
| # then, again, call `m5 exit` to terminate the simulation. After simulation |
| # has ended you may inspect `m5out/system.pc.com_1.device` to see the echo |
| # output. |
| command = "m5 exit;" \ |
| + "echo 'This is running on Timing CPU cores.';" \ |
| + "sleep 1;" \ |
| + "m5 exit;" |
| |
| board.set_kernel_disk_workload( |
| # The x86 linux kernel will be automatically downloaded to the if not |
| # already present. |
| kernel=Resource("x86-linux-kernel-5.4.49"), |
| # The x86 ubuntu image will be automatically downloaded to the if not |
| # already present. |
| disk_image=Resource("x86-ubuntu-18.04-img"), |
| readfile_contents=command, |
| ) |
| |
| simulator = Simulator( |
| board=board, |
| on_exit_event={ |
| # Here we want override the default behavior for the first m5 exit |
| # exit event. Instead of exiting the simulator, we just want to |
| # switch the processor. The 2nd m5 exit after will revert to using |
| # default behavior where the simulator run will exit. |
| ExitEvent.EXIT : (func() for func in [processor.switch]), |
| }, |
| ) |
| simulator.run() |